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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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Journal Archive

2019-10

P.435

[REGULAR PAPER] Approximate Radix-4 Booth Multiplication Circuit

Kibeom Kim;Seokha Hwang;Youngjoo Lee;Sunggu Lee
https://doi.org/10.5573/JSTS.2019.19.5.435
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P.446

[REGULAR PAPER] Orbital Driving and Detection System of Piezoelectric Gyroscopes for Inertia Sensors

Byengleul Lee;Seung Joon Paik;Bonghwan Kim
https://doi.org/10.5573/JSTS.2019.19.5.446
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P.454

[REGULAR PAPER] LDMOS with Variable-k Dielectric for Improved Breakdown Voltage and Specific On-resistance

Songnan Guo;Junji Cheng;Xing Bi Chen
https://doi.org/10.5573/JSTS.2019.19.5.454
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P.461

[REGULAR PAPER] Analog-digital Mixed-mode 10-tap Tomlinson-Harashima Precoding Equalizer for Single-ended High-speed Transmitter

Min-Kyun Chae;Won-Cheol Lee;Eunsung Seo;Young-Soo Sohn;Kwang-Il Park;Byungsub Kim;Jae-Yoon Sim;Hong-June Park
https://doi.org/10.5573/JSTS.2019.19.5.461
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P.470

[REGULAR PAPER] LIGBT-based ESD Protection Device with High Holding Voltage for 15 V Power IC Applications

Kyoung-Il Do;Byeong-Suk Lee;Yong-Seo Koo
https://doi.org/10.5573/JSTS.2019.19.5.470
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P.477

[REGULAR PAPER] A Modified 2-D Vernier Time-to-digital Converter Using Resettable T-latch

Young-Min Jang;Ying He;Sang-Bok Cho;Ji-Hoon Kim;Sung Min Park
https://doi.org/10.5573/JSTS.2019.19.5.477
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P.485

[REGULAR PAPER] Compensation of Transfer Function Mismatch in a Two-stage MASH ADC with a Single SAR Quantizer

Saemin Im;Jong-Yoon Shin;Sang-Gyu Park
https://doi.org/10.5573/JSTS.2019.19.5.485
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P.492

[REGULAR PAPER] A Digital Low-dropout Regulator with A Voltage Differential Detector for Removing Transient Oscillation

Ki-Chan Woo;Byung-Do Yang
https://doi.org/10.5573/JSTS.2019.19.5.492
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P.498

[REGULAR PAPER] A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

Dongmin Kim;Donggu Im;In-Young Lee
https://doi.org/10.5573/JSTS.2019.19.5.498
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P.505

[LETTER] A Low Voltage and Low Power Flip-flop Design Using Virtual VDD Scheme

Jin-Fa Lin;Shao-Wei Yu;Chang-Ming Tsai;Ming-Hwa Sheu
https://doi.org/10.5573/JSTS.2019.19.5.505
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