Mobile QR Code QR CODE

  1. (Department of Electrical and Electronic Eng., University of Ulsan)
  2. (Dept. of Electronic and Electrical Eng., Ewha Womans University)

CMOS, LiDAR, Resettable T-latch, TDC, Vernier.


For the past decades, light detection and ranging(LiDAR) systems have been paid a great deal of attention because of its feasibility to realize autonomous vehicles [1]. In particular, panoramic scan LiDARs have been popular because it can detect the reflected weak light signals from targets located in 360$^{\mathrm{o}}$ directions, measure the distance to all the targets, and eventually visualize three dimensional image of the surrounding scene [2]-[3]. For this purpose, high-sensitivity optical receivers are mandatory to recover the target distance information precisely [4].

Fig. 1 shows the block diagram of a conventional LiDAR systems, where the laser transmitter(Tx) emits light signals to targets, and sends simultaneously a start pulse to time-to-digital converter(TDC) located right after the analog front-end(AFE) circuit of optical receiver(Rx) for the initialization of distance measurements [5]-[10]. Then, the reflected lights from the targets arrive and are detected by a multi-channel optical Rx array that converts the reflected light signals to stop-timing pulses and conveys them to the same TDC with a certain amount of time delay. Finally, the TDC discriminates the time interval between START and STOP pulses, thus estimating the precise distance to targets.

Fig. 1. Block diagram of a typical LiDAR system.



Various TDCs have been previously reported in [11]-[16]. Among these, 1-dimensional flash TDC was the simplest configuration as shown in Fig. 2, which consists of a series of CMOS buffer delay lines and comparators. Thereby, START signals enter the input of the delay line, and pass through the serial delay elements. Namely, START signals are delayed by an integer multiple of the buffer delay(${\tau}$$_{1}$). Therefore, this flash TDC provides the advantages of high-speed timing, single-event timing measurement, and simple digital implementation. However, it consumes large power and occupies large chip area because of the required n delay elements and (n${-}$1) comparators. Yet, its timing resolution is significantly limited.

In order to overcome the limited timing resolution of flash TDCs, Vernier TDC was suggested in [11]-[12]. Fig. 3 depicts the block diagram, in which the delay(${\tau}$$_{1}$) of START signals is larger than that(${\tau}$$_{2}$) of STOP signals. Then, the resolution(${\tau}$$_{1}$ ${-}$ ${\tau}$$_{2}$) of Vernier TDC can be highly precise when compared to the previous flash TDC. Nonetheless, this Vernier TDC consumes inevitably large chip area for long range measurements, hence limiting its usage to cm-level short-reach applications. Besides, the Vernier TDC output can cause comparison errors, especially when the START pulse passes over the STOP pulse.

In order to compensate these walk errors effectively, dual-threshold TDC circuits were developed in [8]-[10]. However, even a single channel of these TDCs occupied large chip area. Also, a timing discriminator was mandatory before the TDC circuits [9]-[10].

Although other various TDCs have been developed, their structures were still complicated and thus unsuitable for long-range LiDARs [14]-[16].

Fig. 2. Flash TDC with timing diagram.


Fig. 3. Vernier TDC with timing diagram.


Fig. 4. 2D Vernier TDC with timing diagram.


In order to save chip area, two-dimensional(2D) Vernier TDC was suggested in [13]. Yet, it has utilized timing comparators as delay cells in its two-dimensional architecture, thereby limiting its operation speeds up to 50 MHz only. Hence, narrow pulses(typ. 3~5 ns) for LiDAR applications could be barely recovered. As shown in Fig. 4, the length of total delay line can be reduced significantly for similar resolution to the 1-D Vernier TDC. However, this 2D Vernier TDC is dependent upon the delay length of input pulses, hence occurring output errors.


In this paper, we propose a modified 2D Verniner TDC which utilizes resettable T-latch circuits. Here, narrow input pulses are converted to wide digital signals, and therefore it can avoid the ambiguity of the pulse overlapping between START and STOP pulses. The resettable T-latch are reset instantly when a second reflected signal arrives. Then, the second narrow pulse is converted to a next wide digital signal for the same process.

Fig. 5. Block diagrams of (a) an original T-latch with its truth table, (b) the proposed resettable T-latch with timing diagrams.


Fig. 5(a) illustrates the block diagram of a typical T-latch that comprises four NAND gates with a clock signal. Its output goes high at a rising edge of input signals when clock is high. Thereafter, the high output is maintained. Even when another consecutive input signal enters, the output state of the T-latch cannot be changed. This operation can be confirmed in the truth table.

On the contrary, Fig. 5(b) depicts the proposed resettable T-latch, where the output state can be reset to zero as soon as another input signal arrives. Also, no clock signals are needed, hence saving power consumption.

The proposed resettable T-latch comprises five NAND gates (NAND5 ~ NAND9), inverter delay-lines, and an XOR gate(XOR1). NAND9 generates a low output at the rising edge of an input pulse, and then is reset to high at the falling edge of the input pulse. Then, the XOR1 compares the high output of Q2 and the inverted reset signal of R’, thereby resetting the final pulse of Q2_OUT.

Fig. 5(b) shows the simulation results, where the proposed resettable T-latch succefully generates the latched high-output with an incoming input signals, is reset when a next input pulse enters, and then maintains high-state after a short reset pulse.

Fig. 6. (a) Block diagrams of the proposed 2D Vernier TDC, and (b) its simulation of delay cell, (c) the errorneous simulation results of a conventional Vernier TDC, and (d) the simulation results of the proposed 2D Vernier TDC with correct digital output codes.


Fig. 6(a) shows the block diagram of the proposed 2D Vernier TDC, where two resettable T-latch circuits are utilized. As aforementioned, since a high-state pulse can be maintained until the arrival of a following input pulse, the output ambiguity of the pulse overlapping between START and STOP signals can disappear in this architecture. Also, with this resettable T-latch, there is no need of dual threshold comparators to measure the time interval, hence omitting the walk error. Only the delay-offset in delay-cells occurs error. The rest of the proposed TDC circuit shares the same architecture to a conventional 2D Vernier TDC.

Fig. 6(b) depicts the simulation results of delay cells, in which no timing offset was assumed. Since each delay cell was designed to provide the delay of 18 ns (${\tau}$$_{\mathrm{1)}}$ and 12 ns (${\tau}$$_{2}$), respectively, the timing resolution of the proposed 2D Vernier TDC becomes 6 ns (= ${\tau}$$_{1}$${-}$${\tau}$$_{2}$) only.

Fig. 6(c) shows the simulation results of a conventional 2D Vernier TDC with the time difference (${\Delta}$T) of 70 ns, where the erroneous bits occur. On the contrary, Fig. 6(d) compares those of the proposed 2D Vernier TDC, demonstrating the effective correction of the error-bits and allowing the maximum time difference (${\Delta}$T) of 90 ns that corresponds to the maximum detection range of 27 meters. It generates the 15-bit output data of 000011111111111, which is finally converted to a 4-bit binary data 1011 via a Thermometer-to-Binary (T2B) encoder.

Hence, as long as the design space of the delay cells is large enough, the proposed 2D Vernier TDC is expected to detect the reflected pulses within the long range of few hundred meters.

Fig. 7. Layout of the proposed 2-D Vernier TDC.


Fig. 7 depicts the layout of the proposed 2D Vernier TDC, where the chip core occupies the area of 0.6 x 0.25 mm$^{2}$. DC simulations reveal the dynamic power dissipation of 0.15 mW from a single 1.2-V supply.

Table 1. Performance comparison of the proposed 2D Vernier TDC with prior arts.






This work*

CMOS tech.(nm)





















Pulse width(ns)







Detection range(m)







# of bits







Timing resolution

20 ps

4.8 ps

1.25 ps

6 ps

8 ps

6 ns

Power diss.(mW)







Core area (mm2)







* post-layout simulations, PD (pseudo-differential delay-line), 2D (two dimensional), TA (time amplifier), GRO (gated ring oscillator), VR (Vernier ring), RTL (resettable T-latch).

PVT corner simulations were conducted to verify the performance variations, yet revealing that the proposed 2D Vernier TDC provides correct operations with less than ${\pm}$8.3-% variation of each rising edge even at the worst-case corners.

Table I summarizes and compares the performance of the proposed 2D Vernier TDC with the previously reported state-of-the-arts. It is clearly seen that the proposed TDC can detect the longest range of 27 meters with the timing resolution of 6 ns from a 15-bit comparator, and consume the lowest power of 0.15 mW.


This paper presents a modified 2-D Vernier TDC utilizing a novel resettable T-latch for LiDAR applications, where narrow input pulses can be converted to a high-latched outputs. Hence, the proposed 2D Vernier TDC is suitable for the detection of the reflected pulses from targets in the long range of few hundred meters.


This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information Technology Research Center) support program (2018-0-01421) supervised by the IITP(Institute for Information & communications Technology Promotion).


Buchbinder E., Speed Detection: LADAR, Search
McLeod D., Jacobson J., Hardy M., Embry C., Sep 2013, Autonomous Inspection using an Underwater 3D LiDAR, IEEE 2013 OCEANS, pp. 1-8Google Search
Vercesi L., Fanori L., Bernardinis F. D., Liscidini A., Castello R., Sep 2018, TOF Lidar Development in Autonomous Vehicle, IEEE Optoelectronics Global Conference, pp. 185-190Google Search
Kim et al. S. G., Nov 2013, A 1.8Gb/s/ch 10mW/ch -23dB crosstalk eight-channel transimpedance amplifier array for LADAR systems, IEEE International SoC Design Conf., pp. 115-118DOI
Kurtti S., Nissinen J., Kostamovaara J., Mar 2017, A Wide Dynamic Range CMOS Laser Radar Receiver With a Time-Domain Walk Error Compensation Scheme, IEEE Trans. on Circuits and Systems I, Vol. 64, No. 3, pp. 550-561DOI
Zheng H., Ma R., Liu M., Zhu Z., Mar 2018, High Sensitivity and Wide Dynamic Range Analog Front-End Circuits for Pulsed TOF 4-D Imaging LADAR Receiver, IEEE Sensors J., Vol. 18, No. 8, pp. 3114-3124DOI
Vornicu I., Carmona-Galan R., Rodriguez-Vazquez A., Jan 2014, A CMOS Imager for Time-of-Flight and Photon Counting Based on Single Photon Avalanche Diodes and In-Pixel Time-to-Digital Converters, Romanian J. of Information Science and Tech., Vol. 17, No. 4, pp. 353-371Google Search
Nissinen J., Nissinen I., Kostamovaara J., May 2009, Integrated Receiver Including Both Receiver Channel and TDC for a Pulsed Time-of-Flight Laser Rangefinder With cm-Level Accuracy, IEEE J. of Solid-State Circuits, Vol. 44, No. 5, pp. 1486-1497DOI
Kurtti S., Kostamovaara J., Jan 2011, An Integrated Laser Radar Receiver Channel Utilizing a Time-Domain Walk Error Compensation Scheme, IEEE Trans. on Instrum. and Meas., Vol. 60, No. 1, pp. 146-157DOI
Cho H. S., Kim C. H., Lee S. G., Oct 2014, A High-Sensitivity and Low-Walk Error LADAR Receiver for Military Application, IEEE Trans. on Circuits and Systems I, Vol. 61, No. 10, pp. 3007-3015DOI
Dudek P., Szczepanski S., Hatfield J. V., Jul 2000, A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line, IEEE J. of Solid-State Circuits, Vol. 35, No. 2, pp. 1626-1635DOI
Staszewski R. B., Vemulapalli S., Vallur P., Wallberg J., Balsara P. T., Mar 2006, 1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS, IEEE Trans. on Circuits and Systems II, Vol. 53, No. 3, pp. 220-224DOI
Vercesi L., Fanori L., Bernardinis F. D., Liscidini A., Castello R., Aug 2010, Two-dimensions Vernier time-to-digital converter, IEEE J. of Solid-State Circuits, Vol. 45, No. 8, pp. 1504-1512DOI
Lee M., Abidi A. A., Apr 2008, A 9b, 1.25ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue, IEEE J. of Solid-State Circuits, Vol. 43, No. 4, pp. 769-777DOI
Straayer M. Z., Perrott M. H., Apr 2009, A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping, IEEE J. of Solid-State Circuits, Vol. 44, No. 4, pp. 1089-1098Google Search
Yu J., Dai F. F., Jaeger R. C., Apr 2010, A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 m CMOS Technology, IEEE J. of Solid-State Circuits, Vol. 45, No. 4, pp. 830-842DOI


Young-Min Jang

Young-Min Jang received the B.S., M.S. degrees from the Department of Electronic and Electrical Engineering, University of Ulsan, Republic of Korea, in 2012, 2014, respectively.

He is currently pursuing the Ph.D. degree at the SoC Lab. in the same university.

His research interests include integrated circuits and architectures for analog/digital CMOS circuit designs for the applications of automotive electronics.

Ying He

Ying He received the B.S. degree in Telecommunications Engineering from Yanbian University of Science & Technology, Yanji, China, in 2012.

She is currently working toward the Ph.D. degree in the analog circuits and systems Lab. at Ewha Womans University.

Her current research interests include integrated circuits and architectures for high-speed CMOS analog front-end designs for optical communication systems.

Sang-Bock Cho

Sang-Bock Cho received the B.S., M.S., and Ph.D. degrees from Hanyang University, Seoul, Republic of Korea, in 1979, 1981, and 1985, respectively, all in electrical engineering.

He has been with the School of Electrical Engineering, University of Ulsan, Ulsan, Republic of Korea, since 1985.

He was with the University of Texas at Austin, Austin, TX, USA, as a Visiting Scholar from 1994 to 1995, and the University of California at San Diego, San Diego, CA, USA, as a Visiting Scholar from 2003 to 2004.

He is currently a Director of the Automobile/Ship Electronics Convergence Center.

His current research interests include VLSI/system-on-chip design and test, computer vision, audio/image signal processing, automotive electronics, and multimedia applications. Dr. Cho is a member of The Institute.

Ji-Hoon Kim

Ji-Hoon Kim received the B.S. (summa cum laude) and Ph.D. degrees in electrical engineering and computer science from KAIST, Daejeon, South Korea, in 2004 and 2009, respectively.

In 2009, he joined Samsung Electronics. In 2018, he joined the faculty of the department of electronic and electrical engineering, Ewha Womans University, where he is currently an associate professor.

His current interests include CPU/DSP, communication modem, and low-power SoC design for security/biomedical systems.

Dr. Kim is a technical committee member of the circuits and systems for communications and VLSI systems and applications in the IEEE Circuits and Systems Society.

He was a recipient of the best design award at Dongbu HiTek IP Design Contest in 2007 and first place award at the International SoC Design Conference Chip Design Contest in 2008.

Sung Min Park

Sung Min Park received the B.S. degree in electrical and electronic engineering from KAIST, Korea, in 1993.

He received the M.S. degree in electrical engineering from University College London, U.K., in 1994, and the Ph.D. degree in electrical and electronic engineering from Imperial College London, U.K., in May 2000.

. In 2004, he joined the faculty of the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea, where he is currently a Professor.

His research interests include high-speed analog/digital integrated circuit designs in submicron CMOS and SiGe HBT technologies for the applications of optical interconnects, silicon photonics, and RF communications.

Prof. Park has served on the technical program committees of a number of international conferences including ISSCC (2004–2009).