I. INTRODUCTION

For the past decades, light detection and ranging(LiDAR) systems have been paid a great deal of attention because of its feasibility to realize autonomous vehicles ^[1]. In particular, panoramic scan LiDARs have been popular because it can detect the reflected weak light signals from targets located in 360$^{\mathrm{o}}$ directions, measure the distance to all the targets, and eventually visualize three dimensional image of the surrounding scene ^[2]-[3]. For this purpose, high-sensitivity optical receivers are mandatory to recover the target distance information precisely ^[4].

Fig. 1 shows the block diagram of a conventional LiDAR systems, where the laser transmitter(Tx) emits light signals to targets, and sends simultaneously a start pulse to time-to-digital converter(TDC) located right after the analog front-end(AFE) circuit of optical receiver(Rx) for the initialization of distance measurements ^[5]-[10]. Then, the reflected lights from the targets arrive and are detected by a multi-channel optical Rx array that converts the reflected light signals to stop-timing pulses and conveys them to the same TDC with a certain amount of time delay. Finally, the TDC discriminates the time interval between START and STOP pulses, thus estimating the precise distance to targets.

Fig. 1. Block diagram of a typical LiDAR system.

II. CONVENTIONAL TDCS

Various TDCs have been previously reported in ^[11]-[16]. Among these, 1-dimensional flash TDC was the simplest configuration as shown in Fig. 2, which consists of a series of CMOS buffer delay lines and comparators. Thereby, START signals enter the input of the delay line, and pass through the serial delay elements. Namely, START signals are delayed by an integer multiple of the buffer delay(${\tau}$$_{1}$). Therefore, this flash TDC provides the advantages of high-speed timing, single-event timing measurement, and simple digital implementation. However, it consumes large power and occupies large chip area because of the required n delay elements and (n${-}$1) comparators. Yet, its timing resolution is significantly limited.

In order to overcome the limited timing resolution of flash TDCs, Vernier TDC was suggested in ^[11]-[12]. Fig. 3 depicts the block diagram, in which the delay(${\tau}$$_{1}$) of START signals is larger than that(${\tau}$$_{2}$) of STOP signals. Then, the resolution(${\tau}$$_{1}$ ${-}$ ${\tau}$$_{2}$) of Vernier TDC can be highly precise when compared to the previous flash TDC. Nonetheless, this Vernier TDC consumes inevitably large chip area for long range measurements, hence limiting its usage to cm-level short-reach applications. Besides, the Vernier TDC output can cause comparison errors, especially when the START pulse passes over the STOP pulse.

In order to compensate these walk errors effectively, dual-threshold TDC circuits were developed in ^[8]-[10]. However, even a single channel of these TDCs occupied large chip area. Also, a timing discriminator was mandatory before the TDC circuits ^[9]-[10].

Although other various TDCs have been developed, their structures were still complicated and thus unsuitable for long-range LiDARs ^[14]-[16].

Fig. 2. Flash TDC with timing diagram.

Fig. 3. Vernier TDC with timing diagram.

Fig. 4. 2D Vernier TDC with timing diagram.

In order to save chip area, two-dimensional(2D) Vernier TDC was suggested in ^[13]. Yet, it has utilized timing comparators as delay cells in its two-dimensional architecture, thereby limiting its operation speeds up to 50 MHz only. Hence, narrow pulses(typ. 3~5 ns) for LiDAR applications could be barely recovered. As shown in Fig. 4, the length of total delay line can be reduced significantly for similar resolution to the 1-D Vernier TDC. However, this 2D Vernier TDC is dependent upon the delay length of input pulses, hence occurring output errors.

III. PROPOSED 2D VERNIER TDC

In this paper, we propose a modified 2D Verniner TDC which utilizes resettable T-latch circuits. Here, narrow input pulses are converted to wide digital signals, and therefore it can avoid the ambiguity of the pulse overlapping between START and STOP pulses. The resettable T-latch are reset instantly when a second reflected signal arrives. Then, the second narrow pulse is converted to a next wide digital signal for the same process.

Fig. 5. Block diagrams of (a) an original T-latch with its truth table, (b) the proposed resettable T-latch with timing diagrams.

Fig. 5(a) illustrates the block diagram of a typical T-latch that comprises four NAND gates with a clock signal. Its output goes high at a rising edge of input signals when clock is high. Thereafter, the high output is maintained. Even when another consecutive input signal enters, the output state of the T-latch cannot be changed. This operation can be confirmed in the truth table.

On the contrary, Fig. 5(b) depicts the proposed resettable T-latch, where the output state can be reset to zero as soon as another input signal arrives. Also, no clock signals are needed, hence saving power consumption.

The proposed resettable T-latch comprises five NAND gates (NAND5 ~ NAND9), inverter delay-lines, and an XOR gate(XOR1). NAND9 generates a low output at the rising edge of an input pulse, and then is reset to high at the falling edge of the input pulse. Then, the XOR1 compares the high output of Q2 and the inverted reset signal of R’, thereby resetting the final pulse of Q2_OUT.

Fig. 5(b) shows the simulation results, where the proposed resettable T-latch succefully generates the latched high-output with an incoming input signals, is reset when a next input pulse enters, and then maintains high-state after a short reset pulse.

Fig. 6. (a) Block diagrams of the proposed 2D Vernier TDC, and (b) its simulation of delay cell, (c) the errorneous simulation results of a conventional Vernier TDC, and (d) the simulation results of the proposed 2D Vernier TDC with correct digital output codes.

Fig. 6(a) shows the block diagram of the proposed 2D Vernier TDC, where two resettable T-latch circuits are utilized. As aforementioned, since a high-state pulse can be maintained until the arrival of a following input pulse, the output ambiguity of the pulse overlapping between START and STOP signals can disappear in this architecture. Also, with this resettable T-latch, there is no need of dual threshold comparators to measure the time interval, hence omitting the walk error. Only the delay-offset in delay-cells occurs error. The rest of the proposed TDC circuit shares the same architecture to a conventional 2D Vernier TDC.

Fig. 6(b) depicts the simulation results of delay cells, in which no timing offset was assumed. Since each delay cell was designed to provide the delay of 18 ns (${\tau}$$_{\mathrm{1)}}$ and 12 ns (${\tau}$$_{2}$), respectively, the timing resolution of the proposed 2D Vernier TDC becomes 6 ns (= ${\tau}$$_{1}$${-}$${\tau}$$_{2}$) only.

Fig. 6(c) shows the simulation results of a conventional 2D Vernier TDC with the time difference (${\Delta}$T) of 70 ns, where the erroneous bits occur. On the contrary, Fig. 6(d) compares those of the proposed 2D Vernier TDC, demonstrating the effective correction of the error-bits and allowing the maximum time difference (${\Delta}$T) of 90 ns that corresponds to the maximum detection range of 27 meters. It generates the 15-bit output data of 000011111111111, which is finally converted to a 4-bit binary data 1011 via a Thermometer-to-Binary (T2B) encoder.

Hence, as long as the design space of the delay cells is large enough, the proposed 2D Vernier TDC is expected to detect the reflected pulses within the long range of few hundred meters.

Fig. 7. Layout of the proposed 2-D Vernier TDC.

Fig. 7 depicts the layout of the proposed 2D Vernier TDC, where the chip core occupies the area of 0.6 x 0.25 mm$^{2}$. DC simulations reveal the dynamic power dissipation of 0.15 mW from a single 1.2-V supply.

PVT corner simulations were conducted to verify the performance variations, yet revealing that the proposed 2D Vernier TDC provides correct operations with less than ${\pm}$8.3-% variation of each rising edge even at the worst-case corners.

Table I summarizes and compares the performance of the proposed 2D Vernier TDC with the previously reported state-of-the-arts. It is clearly seen that the proposed TDC can detect the longest range of 27 meters with the timing resolution of 6 ns from a 15-bit comparator, and consume the lowest power of 0.15 mW.

IV. CONCLUSIONS

This paper presents a modified 2-D Vernier TDC utilizing a novel resettable T-latch for LiDAR applications, where narrow input pulses can be converted to a high-latched outputs. Hence, the proposed 2D Vernier TDC is suitable for the detection of the reflected pulses from targets in the long range of few hundred meters.