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Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures

(Junsu Yu) ; (Byung-Gook Park) ; (Dae Woong Kwon)

To investigate the effects of various pillar conditions such as pillar thickness (Tpillar), pillar height (TSi), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFETVS) and AC switching characteristics of TFETVS inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the Tpillar is thicker, 2) the TSi is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (CGD)-gate voltage (VG) curve becomes positive-shifted due to the weaker controllability of VG on the drain-side channel. Through the transient responses of TFETVS inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted CGD-VG curve caused by the weaker VG controllability on the drain-side channel.

A Low-overhead Solution for Obfuscating Scan Data Against Scan-based Side-channel Attacks

(Xiong Zheng) ; (Zuoting Ning) ; (Weizheng Wang) ; (Yan Peng)

Scan-based design has been used normally to simplify the manufacturing test. However, the convenience brought by the design also becomes the weakness that increases the vulnerability of crypto chips. Many attacks have been proved effective to steal secret information stored inside chips through this structure. In this paper, we will propose a secure scan design with very low overhead and high security. The proposed scheme chooses some scan cells in the front part of the original scan chain to store the test key. The output of these scan cells will be transmitted to a multiple-input AND gate to realize authentication. If the input test key is incorrect, the data of the sub-chain in the front part of the scan chain will be shifted circularly and the values of those scan cells used to store the test key will be dynamically transmitted to the latter part of the scan chain to realize dynamic data obfuscation. The scheme excellently resists existing scan attacks.

A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling

(Jae-Geun Lim) ; (Je-Min Jeon) ; (Jun-Ho Boo) ; (Yoon-Bin Im) ; (Jae-Hyuk Lee) ; (Sung-Han Do) ; (Young-Jae Cho) ; (Michael Choi) ; (Gil-Cho Ahn) ; (Seung-Hoon Lee)

This work proposes two versions of a 12 b 100 MS/s successive-approximation register (SAR) ADC based on a non-binary C-R hybrid DAC. The proposed DAC applies a non-binary weighted capacitor array to the 7 MSBs to meet the settling requirement of the DAC output and determines the remaining 5 LSBs using the reference voltages generated from a simple resistor string to reduce the DAC area significantly. The Version 1 ADC in a 28 nm CMOS adopts a synchronous SAR logic and a comparator with a tail capacitor and a reset switch to minimize power consumption. The Version 2 ADC in a 0.18 μm CMOS employs an asynchronous SAR logic with simple meta-stability correction logic to achieve high-speed operation. The Version 1 ADC which has an active die area of 0.042 mm2 shows a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 62.3 and 77.3 dB, respectively, consuming 1.3 mW with a 1.0 V supply voltage. The Version 2 ADC is based on a similar analog circuit topology, showing a maximum SNDR and SFDR of 60.1 and 73.5 dB, respectively, with an active die area of 0.30 mm2, operating at a 1.8 V supply voltage.

A Wideband Sub-GHz Receiver Front-end Supporting High Sensitivity and Selectivity Mode

(Ilku Nam) ; (Ockgoo Lee) ; (Donggu Im)

A low noise and highly linear wideband RF front-end circuit for sub-GHz Internet of Things (IoT) applications is proposed. The proposed front-end is composed of a broadband single-ended LNA, a wideband differential LNA employing thermal noise cancellation technique, and an in-phase and quadrature (I/Q) linearized harmonic rejection mixer (HRM). Depending on the interference environment, the proposed front-end supports two operation modes having high sensitivity and selectivity performance by enabling or disabling the first building block of the single-ended LNA. At high sensitivity mode, the front-end shows a voltage gain (Av) of greater than 38 dB, a noise figure (NF) of less than 2.1 dB, an input-referred third-order intercept point (IIP3) of greater than -23 dBm, and an input-referred second-order intercept point (IIP2) of greater than +15 dBm in the sub-GHz frequency band. Concerning for high selectivity mode, it achieves an Av of greater than 22.5 dB, a NF of less than 4.7 dB, an IIP3 of greater than ?6.8 dBm, and an IIP2 of greater than +50 dBm over the same operating frequency range.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

(Kyoung-Il Do) ; (Byung-Seok Lee) ; (Seung-Hoo Jin) ; (Yong-Seo Koo)

This paper proposes a design for a whole-chip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 μm bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

A 24 GHz CMOS Receiver Front-end for In-Cabin Radar Systems

(Yangji Jeon) ; (Suyeon Lee) ; (Jinman Myung) ; (Geonwoo Park) ; (Seungjik Lee) ; (Ockgoo Lee) ; (Hyunwon Moon) ; (Ilku Nam)

A 24-GHz direct-conversion receiver front-end is presented for in-cabin applications. The proposed RF receiver is composed of a low-noise amplifier, an I/Q down-conversion mixer, and an I/Q local oscillator (LO) generator circuit. An inverter -type transconductor with third-order nonlinearity cancellation is applied to the I/Q down-conversion mixer to improve the linearity of the I/Q down-conversion mixer. By adopting a linear I/Q down-conversion mixer and a balanced I/Q LO generator, the 24 GHz receiver front-end obtains high linearity and good I/Q balancing performance. The receiver front-end draws 21-mA current from a 1.2-V supply voltage. It shows a conversion gain of 30.4 dB, noise figure (NF) of 4.5 dB, and an input 1-dB compression point (input P1dB) of -23 dBm in the 24-24.5 GHz range.

An Integrated Circuit for Biphasic Pulse Generator with Variable Parameters

(Shinyong Shim) ; (Jaehoon Sung) ; (Sung June Kim)

A biphasic pulse generator integrated circuit (IC) was designed, and the parameters of the generated pulses such as pulse rate, duration, and amplitude were adjusted to the desired values by using the time-varying differences of two inputs of the operational amplifier integrated on the IC. The chip was fabricated with the MagnaChip /SK Hynix CMOS 0.35 μm process, which allowed a maximum pulse amplitude of 3.3 V. In addition, it included a transformer that allowed the IC to rectify the amplitude modulated (AM) input with a 1 Ghz carrier and provide the supply voltage to generate the pulses. The whole size of the full system was 441.5 μm×527.8 μm, and the system successfully generates biphasic pulses up to 1.2 kHz using the RF signal. This circuit can be used to generate biphasic pulses with variable parameters for distributed neural interfaces, and to provide scan voltages for potentiostat applications such as in the Fast Scan Cyclic Voltammetry (FSCV). In addition, this IC with an integrated transformer suggests that a wireless electroanalytical system on a chip can be achieved as a future work.

High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

(Nahyun Kim) ; (Junyoung Song)

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ns response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 dB is obtained when the load current is 10 mA. The circuit is implemented in 65-nm CMOS process.