Mobile QR Code QR CODE

A Design of Whole-chip ESD Protection Circuit with SCR-based I/O and LIGBT-based Power Clamp

https://doi.org/10.5573/JSTS.2021.21.1.001

(Kyoung-Il Do) ; (Yong-Seo Koo)

This study proposed and fabricated an all-directional whole-chip electrostatic discharge (ESD) protection circuit design, including input/output (I/O) and power clamps. The proposed I/O ESD clamp is based on silicon controlled rectifiers (SCR) and possesses improved snapback and bidirectional characteristics owing to the insertion of an improved floating region. The proposed ESD power clamp has an excellent clamping ability and a high holding voltage owing to the use of a lateral insulated gate bipolar transistor (LIGBT). The ESD protection circuit is fabricated using a 0.18 μm bipolar-CMOS-DMOS (BCD) process and is properly placed in the ESD clamp position. Consequently, the proposed ESD protection circuit contributes toward improving the area efficiency and reliability of the integrated circuit. The electrical properties and robustness were analyzed using a transmission line pulse (TLP) system and an ESD pulse generator. According to the measurements, the proposed whole-chip ESD protection circuit is robust enough to discharge 8 kV HBM and 800 V MM in four ESD stress modes for the input and output units (PD: positive -VDD, ND: negative -VDD, PS: positive -VSS, and NS: negative -VSS) as well as in the DS (VDD to VSS) mode between VDD and VSS.

A Time-based Transceiver Front-end Circuit with 1-tap IIR DFE and Relaxed Termination for Short-reach PCB Interconnect

https://doi.org/10.5573/JSTS.2021.21.1.009

(Min-Kyun Chae) ; (Seung-Jun Bae) ; (Jung-Hwan Choi) ; (Kwang-Il Park) ; (Jung-Bae Lee) ; (Hong-June Park)

A time-based low-power transceiver is proposed for short-reach PCB interconnect which connects two chips closely placed on a printed circuit board (PCB). This was achieved by reducing the I/O signaling power of transmitter (TX) with the increase of on-die termination (ODT) resistance. The short-reach PCB interconnect is approximated as a single-time-constant RC channel due to the large ODT resistance. The increase of inter-symbol interference (ISI) by the increased R-C time constant of channel was compensated by using a 1-tap infinite-impulse-response (IIR) decision-feedback equalizer (DFE) at receiver (RX). The RX circuit is composed of a cascaded connection of a voltage-to-time converter, an IIR DFE, a FIR DFE and a time comparator. The transceiver chip was implemented in 65 nm CMOS technology; in tests with a 1.6-mm micro-strip line channel the transceiver achieved maximum data-rate of 12 Gb/s at 0.8 V supply and minimum energy efficiency of 0.37 pJ/b at 8 Gb/s and 0.75 V supply.

The Fabrication of Floating Gate CMUT with Multi Cantilevers and Its Failure Analysis

https://doi.org/10.5573/JSTS.2021.21.1.021

(Jiajun Liu) ; (Benxian Peng) ; (Fengqi Yu)

In order to realize soft grasp of robot manipulator, distance sensors need to be installed in the robotic fingers. CMUT (Capacitive Micro-machined Ultrasonic Transducer), which owns advantages of extra small size and excellent dielectric impedance matching, meets the demand very well. However there are some difficulties in design and fabrication of a CMUT device. In this paper we propose a novel CMUT design technique based on the integration of standard 0.18 um CMOS process and MEMS process. The design and post processing of CMUT is explained in detail. The fabricated CMUT is tested. It is found that the signal is not detected from some devices. Therefore, the failure analysis of CMUT is carried out in some aspects. Finally, fatigue failure is determined as the cause of the failure.

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing

https://doi.org/10.5573/JSTS.2021.21.1.029

(Kenta Nishiguchi) ; (Toshiyuki Inoue) ; (Rei Yamazaki) ; (Kazunori Ogohara) ; (Akira Tsuchiya) ; (Keiji Kishine)

In an FPGA-based image processing system, memory access plays an important role in increasing the speed of image processing. With the conventional method, the memory access interval for image processing was fixed, which limited the processing speed. In this work, we developed a novel memory access method that dynamically controls the intervals between memory access requests for image processing by monitoring the memory status. We implemented an image processing system with the proposed method and examined its characteristics. The maximum processing speed with the proposed method reached 30.7 fps, which was 1.65 times faster than that of the conventional method.

Low Frequency Noise Modeling and SPICE Implementation of Nanoscale MOSFETs

https://doi.org/10.5573/JSTS.2021.21.1.039

(Jonghwan Lee)

The physics-based compact gate and drain current noise models of nanoscale MOSFETs at low frequencies are presented. The models are primarily developed to be implemented in circuit simulators and are further applied to gain insight into the noise behavior of advanced MOSFETs. For a comprehensive evaluation of noise performance at low frequencies, the models describe all the important physical noise sources and effects which are observed in nanoscale MOSFETs with ultrathin gate oxides. The models account for the gate leakage current noise, the drain current noise, cross correlation effects between the gate and the drain, and quantum mechanical (QM) effects in the inversion layer. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format and are validated through a comparison of simulation results and measurements.

Multi Look-up Table FPGA Reverse Engineering with Bitstream Extraction and Multiple PIP/PLP Matching

https://doi.org/10.5573/JSTS.2021.21.1.049

(Hoyoung Yu) ; (Mannhee Cho) ; (Sangil Lee) ; (Hyungmin Lee) ; (Young-Min Kim)

Owing to the recognition of the field-programmable gate array (FPGA) as a key component of Internet of Things (IoT) devices, there has been exponential growth in the demand for FPGAs. Along with this increased demand, FPGA security issues have also drawn significant attention. An attacker can extract bitstream, the configuration data stored in FPGAs, and manipulate it to insert a malicious circuit (e.g., Trojan attack). To prevent such attacks, it is essential to identify their root cause and implement countermeasures. In this study, we target Xilinx FPGAs, which provides two FPGA design software, Integrated Software Environment (ISE) design suite and Vivado design suite, depending on the FPGA family. While FPGA reverse engineering has been studied extensively using ISE, little work has been done on Vivado environment. No research has been conducted on the reverse engineering of programmable interconnect points (PIPs), which is essential for reverse engineering of complete circuit. In this study, we propose an FPGA reverse engineering method using the latest Vivado design suite environment FPGAs to extract complete circuits by combining both logic data from programmable logic points and signal connectivity data from PIPs extracted from the bitstream. We performed reverse engineering of 3-bit adder circuit targeting an ARTIX-7 family chip, using Verilog and Vivado design suite. It was confirmed that the logic recovered from bitstream is identical to the actual 3-bit adder circuit, verifying 100% recovery rate of the proposed reverse engineering method.

Ferroelectricity in Al2O3/Hf0.5Zr0.5O2 Bilayer Stack: Role of Dielectric Layer Thickness and Annealing Temperature

https://doi.org/10.5573/JSTS.2021.21.1.062

(Dipjyoti Das) ; (Venkateswarlu Gaddam) ; (Sanghun Jeon)

In this paper, we investigate the ferroelectric properties of Al2O3/Hf0.5Zr0.5O2 (HZO) dielectric/ferroelectric (DE/FE) bilayer stack for different DE layer thickness and annealing temperature. The DE/FE stack showed enhanced remanent polarization (Pr) as compared to the reference HZO capacitor for very thin DE layer due to the charge induced by the leakage current through the DE layer. On the contrary, for higher DE layer thickness, this charge injection is suppressed and the ferroelectricity in the DE/FE stack reduces due to the involvement of the depolarization field. An increase in the coercive field (Ec) of the DE/FE based capacitors was observed with increasing the DE layer thickness. Moreover, the Pr value of both HZO and DE/FE stack increases with increasing the annealing temperature till 800 oC and decrease thereafter. The addition of Al2O3 layer increases the thermal stability of the capacitors and despite the HZO capacitors being degraded at annealing temperature beyond 800 oC, the DE/FE stack-based capacitors were found to demonstrate descent ferroelectricity.

A Low-luminance Compensation Current Driver for AMOLED Displays

https://doi.org/10.5573/JSTS.2021.21.1.068

(Seonwoo Yeom) ; (Minhyun Jin) ; (Donggun Lee) ; (Kyujin Kim) ; (Soo Youn Kim)

A Feedback Trans-conductance (FB-Gm) current-mode driver with a charge-transfer circuit is proposed to achieve ultra-low current drivability (≤ 2 nA). By using an FB-Gm current-mode driver, both threshold-voltage and mobility variations can be compensated. In addition, an initialization technique that uses a charge-transfer circuit is proposed to handle an ultra-low current of approximately 2 nA with fast driving speed. The simulation results show that the proposed current-mode driver can compensate for 2 nA of current within 10 μs of one-row time with 10 μA/channel of static-current consumption. Here, 1.5 kΩ of series resistance and 25 pF of shunt capacitance, which represent double-wide ultra XGA (DWUXGA) AMOLED displays, are used for accurate simulation.

A 62.6-pJ/Conversion Temperature Sensor with a Capacitor Voltage Division

https://doi.org/10.5573/JSTS.2021.21.1.073

(Bumjin Park) ; (Youngwoo Ji) ; (Jae-Yoon Sim)

This paper presents an ultra-low-power temperature sensor that detects the temperature with a leakage-based bandgap circuit and converts it with an asynchronous SAR ADC. The implemented temperature sensor consumes 487 pW at 20 ºC with an energy efficiency of 62.6 pJ/conversion. A 1-point and 2-point calibrations show peak-to-peak inaccuracies of -3.43/+2.77 ºC and -1.63/+1.63 ºC, respectively, in a temperature range of -30-to-100 ºC. The supply sensitivity is 0.61 ºC/V at 20 ºC.

Photoresponsivity Enhancement of AlGaN/GaN Heterojunction Phototransistor with ZnO Nanodot Coating Layer

https://doi.org/10.5573/JSTS.2021.21.1.080

(Won-Ho Jang) ; (June-Heang Choi) ; (Chang-Yeol Han) ; (Heesun Yang) ; (Ho-Young Cha)

The effects of a ZnO nanodot coating layer on the photoresponsivity characteristics of an AlGaN/GaN heterojunction phototransistor was investigated. The ZnO nanodot layer was introduced on the detection surface of the phototransistor using a simple spin-coating process. The ZnO nanodot layer not only reduced the dark current but also significantly increased the photoresponsivity. At the wavelength of 300 nm, the photoresponsivity increased from 1.02 × 106 to 1.76 × 106 A/W.