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Implementation and Performance Analysis of Elliptic Curve Cryptography using an Efficient Multiplier

https://doi.org/10.5573/JSTS.2022.22.2.53

(Renita J.) ; (Edna Elizabeth N.) ; (Nandhini Asokan)

In Elliptic Curve Cryptography (ECC), modular multiplication in a finite field is a resource-consuming operation. The design of an efficient multiplier for ECC implementation in FPGA is an ever-evolving research problem. In this paper, we provide an efficient implementation of ECC for GF (2233) in FPGA. We propose a hybrid Karatsuba multiplier which is found to be occupying lesser slices compared to other optimized Karatsuba multiplier in [1]. This, in turn, amends the efficiency of the ECC processor in the FPGA platform. The proposed processor is implemented in ZedBoard containing Xilinx XC7Z020-1CLG484C Zynq-7000 AP SoC. In comparison with other similar works, the implementation results of ECC show consequential competitiveness in hardware efficiency and we obtain an efficient multiplier and ECC processor realized in FPGA. From the application point of view, ZedBoard has an ARM Processor and hence this can be utilized in vehicle On-Board Units (OBU) because of its lightweight properties.

Doping-less Tunnel Field-effect Transistor with a Gate Insulator Stack to Adjust Tunnel Barrier

https://doi.org/10.5573/JSTS.2022.22.2.61

(Min Gyu Jeon) ; (Kang Lee) ; (Sangwan Kim) ; (Garam Kim) ; (Jang Hyun Kim)

This paper suggests a doping-less TFET that shows high performance in low power circumstances and its electrical characteristics are analyzed. The doping-less TFET’s gate insulator consists of ONO (SiO2-Si3N4-SiO2) triple dielectric. When programmed, the tunnel barrier is formed by electron charge traps of nitride region. Then, the tunnel barrier is adjusted by trapped electrons in silicon nitride region. Therefore, it is possible to control the electrical characteristics of the device by controlling the number of electrons trapped in the nitride region by adjusting the program time. However, since the device is made of doping-less, the depletion area has increased as the substrate thickness due to the loss of control of the gate. So, the thinner the substrate thickness of the device, the better the efficiency. In the case of thin substrate thickness, TCAD simulation was per-formed by applying a 5 nm of substrate thickness because the thinner the substrate thickness of the device, the more efficient it is. As a result, the proposed device shows low subthreshold swing (SS) of 29.01 mV/decade at 0.5 V of VDS in the transfer curves. Then, the proposed TFET can control the electrical characteristics with program time and can be driven with low power due to having a low SS.

Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm

https://doi.org/10.5573/JSTS.2022.22.2.69

(Shuo Cai) ; (Sicheng Wu) ; (Weizheng Wang) ; (Fei Yu) ; (Lairong Yin)

With the development of microelectronics technology, the feature size of integrated circuit continues to shrink, and circuit performance has been improved. At the same time, however, factors such as process disturbance, power noise, and particle radiation are having an increasingly serious influence on the Failure Probability of Circuits (FPC). Searching the input vectors that are sensitive to FPC can assist circuit designers in selectively reinforcing the circuit to reduce the fault-tolerant overhead and improve the fault-tolerant efficiency. In this paper, an Improved Adaptive Cuckoo Search (IACS) algorithm is proposed to search sensitive circuit vectors. The vector segmentation strategy is used to change the dimension of the input vector, the hill climbing algorithm is used to improve the quality of the initial population, and the adaptive strategy is used to control parameters such as power-law index, discovery probability and scaling factor. At the same time, a Correlation Separation Approach (COSEA) is proposed to calculate the FPC under specific vector excitation. Experimental results show that the proposed algorithm has higher accuracy and better efficiency compared with existing algorithms.

A Compact Macromodeling Method for Characterizing Large-signal DC and AC Performance of InP and GaAs HBTs

https://doi.org/10.5573/JSTS.2022.22.2.84

(Lin Cheng) ; (Hongliang Lu) ; (Yuming Zhang) ; (Yimen Zhang)

In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) is proposed and successfully applied to describe the DC and AC performance of InP and GaAs HBT devices. Using the Symbolically-defined Device (SDD) technology, an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network is established. The empirical current and charge functions are embedded in the SDD macro circuit network module. Compared with other large-signal models, the proposed model description and the relevant parameter extraction are relatively simpler, and at the same time, this method can maintain high fitting accuracy. To assess the validity and the accuracy of the proposed model, the compact large-signal model is constructed for 1 μm InP HBT and 1 μm GaAs HBT. Based on the complete extraction of the model parameters, excellent consistency is obtained between the measured and modeled results.

Measurement and Characterization of Unstable Pixels of Long-wavelength HgCdTe Infrared Focal Plane Array

https://doi.org/10.5573/JSTS.2022.22.2.93

(Yu Zhang) ; (Songmin Zhou) ; (Xun Li) ; (Xi Wang) ; (Liqi Zhu) ; (Chun Lin)

Unstable pixels directly affect the imaging quality of the long-wavelength infrared (LWIR) mercury cadmium telluride (HgCdTe, MCT) focal-plane-array (FPA) detector. This study investigates the unstable pixels of LWIR HgCdTe linear arrays with different passivation. According to the different fluctuation characteristics, the unstable pixels are classified into four types: trend-clear type (including the rising and declining pixels), fluctuating type, comb type, and telegraph type. The number of unstable pixels under different bias voltage is counted, which indicates that when the bias voltage is large enough, the number of unstable pixels can increase sharply. By comparing the characteristics of the unstable pixels of two linear arrays with different passivation, we find that the unstable pixels are sensitive to the surface passivation. In addition, the dark currents of unstable pixels and that of normal pixels are compared, inferring that there is no apparent connection between the cause of the instability of the pixels and that of the dark current.

Prediction Methodology for Next-generation Device Characteristics using Machine Learning

https://doi.org/10.5573/JSTS.2022.22.2.101

(Gwangnae Gil) ; (Sola Woo)

In this article, we propose a prediction methodology for next-generation device characteristics for process design kit (PDK) models that utilize various machine learning algorithms to achieve high accuracy and reduction of development turn-around time (TAT). The Berkeley short-channel IGFET model (BSIM) is used for generating datasets, while n-channel MOSFET compact model is used for peripheral circuits in dynamic random-access memory (DRAM) technology. Datasets for training comprise device characteristics that use compact models in present-generation products. In addition, a compact model of next-generation products is used for validating datasets. We demonstrate that our prediction methodology using random forest regression provides high accuracy of less than 0.7% RMSE and reduces development TAT.

Fabrication and Performances of Recessed Gate AlGaN/GaN MOSFETs with Si3N4/TiO2 Stacked Dual Gate Dielectric

https://doi.org/10.5573/JSTS.2022.22.2.105

(Jaewon Jang) ; (Jin-Hyuk Bae) ; (Sin-Hyung Lee) ; (In Man Kang)

In this paper, a recessed gate AlGaN/GaN metal-oxide-semiconductor field-effect-transistor (M-OSFET) with Si3N4/TiO2 stacked dual gate dielectric was proposed and fabricated to improve the current drivability. Normally-off operation with a Vth of 1.81 V was obtained using a Cl2-based gate recess etching process. Dual gate dielectric technology was used to improve the current characteristics that can be degraded by damage resulting from gate recess etching. Compared to the single gate dielectric (Si3N4 = 30 nm)-based device, the ID,max and gm of the dual gate dielectric (Si3N4/TiO2 = 10/20 nm)-based device were improved by 292% and 195%, respectively. Moreover, the Ron and SS were improved by 62% and 68%, respectively. Breakdown voltage decreased by 1.4%, but there was minor difference. Therefore, the technique of depositing Si3N4 on GaN and then stacking high-k TiO2 can improve the current characteristics by increasing the capacitance through a simple process. As such, the recessed gate AlGaN/GaN MOSFETs with Si3N4/TiO2 stacked dual gate dielectric has the potential for high-efficiency power devices.

Review of Analog Neuron Devices for Hardware-based Spiking Neural Networks

https://doi.org/10.5573/JSTS.2022.22.2.115

(Dongseok Kwon) ; (Sung Yun Woo) ; (Jong-Ho Lee)

To process data operations more efficiently in deep neural networks (DNNs), studies on spiking neural networks (SNNs) have been conducted. In the reported literature, CMOS neuron circuits that mimic the biological behavior of an integrate-and-fire function of neurons have been mainly studied. Because conventional neuronal circuits need to be improved in terms of area and energy consumption, neuron devices with memory functions such as resistive random access memory (RRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), floating body FETs, and ferroelectric FETs have been emerged to replace a membrane capacitor and trigger device in the conventional neuron circuits. In this review article, neuron devices that can increase the integration density of conventional neuronal circuits and reduce power consumption are reviewed. These devices are expected to play an important role in future neuromorphic systems.