https://doi.org/10.5573/JSTS.2024.24.3.165

(Monalisa Pandey) ; (Aminul Islam)

Memory circuits in the space environment are susceptible to stability and reliability issues caused by charged particles such as α-particles, heavy-ions, electrons, and photons. These particles can create an ion track inside the memory device, leading to an upset in the storage bit. This poses a significant problem for conventional 6T SRAM, which is unable to tolerate such upsets. To address this issue, several authors have proposed radiation-hardened SRAM cells to mitigate the upset problem. This paper proposes a 12 transistor-based SRAM cell, the performance parameters of which have been compared with the other referenced memory cells like conventional 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO SRAM cells. The proposed design exhibits high resilience to radiation disturbances. Additionally, it boosts a critical charge (QC) of 1.6 fC, positioning it as a highly favorable option for deep space applications.The proposed 12T shows higher read stability which is validated by RSNM. Our proposed design shows 2×, 1.6×, 1.4×, and 1.2× higher RSNM than that of the 6T, QUATRO 10T, QUCCE 12T and WEQUATRO SRAM cells. The proposed cell also exhibits lower hold power consumption compared to QUATRO 10T (0.86×), QUCCE 12T (0.40×), and WEQUATRO (0.74×), respectively. Similarly, in terms of area overhead proposed 12T consumes smaller area than WEQUATRO and QUCCE 12T, respectively. Major design metrics such as critical charge (QC), write ability (determined by Combined Word Line Margin (CWLM)), read stability (determined by RSNM), Hold Power dissipation (HPWR), Read Access Time (TRA), Write Access Time (TWA), area, etc., are conflicting in nature (meaning one can be improved at the expense of another). Therefore, a new design metric called Electrical Quality Metric (EQM) has been developed based on these design metrics. The proposed 12T SRAM cell exhibits the highest value of EQM, proving its superiority to other comparison SRAM cells.

https://doi.org/10.5573/JSTS.2024.24.3.179

(Jong Kyung Park) ; (Seul Ki Hong)

We have developed a process for the efficient implementation of short channel devices using a lift-off self-align structure, which simultaneously implements the gate stack(dielectric / electrode) and spacer. By utilizing the lift-off process in a semiconductor device structure with 2-D materials as the channel, we have experimentally verified the stable implementation of short channel lengths down to the level of 50 nm using AFM/SEM. Furthermore, through analysis of the drain current, we have confirmed the improvement in electrical characteristics by applying the self-align technique to structures with the same channel length. The proposed method in this study can offer efficient value in research activities such as device structure and property development in the field of device research, providing a more efficient and cost-saving process.

https://doi.org/10.5573/JSTS.2024.24.3.184

(Goohyung Chung) ; (Kyoungub Cho) ; (Taehyoun Oh)

A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb/s. The prototype chip has been fabricated in 65 nm CMOS process and occupies 1.02 mm2 die area. The transceiver consumes 72 mW/lane from 1.2 V supply. The measured eye-openings show 28.7% improvement vertically in Tx output by pre-emphasis at 6.4 Gb/s. The built-in Rx BER counter shows 0.25 unit interval (UI) horizontal eye-opening improvement at 10-9 BER in this speed.

https://doi.org/10.5573/JSTS.2024.24.3.191

(Chang-Hyeon Lee) ; (Jae-Hyeok Lee) ; (Haesung Jung) ; (Hanyoung Lee) ; (Hanho Lee)

This paper presents the design of the post-quantum secure encryption algorithm, Crystals?Kyber, a next-generation public key encryption system based on high-level synthesis (HLS). Furthermore, we propose a hardware/software (HW/SW) co-design approach and a hybrid HLS-RTL design to implement the Crystals?Kyber post-quantum secure encryption system and present the corresponding results. In the HW/SW co-design, we optimized the Crystals?Kyber intellectual property core using HLS for the HW component, while the SW component was implemented on the Xilinx ZYNQ 104 FPGA using Xilinx's PYNQ platform with Python host code. The hybrid design enhanced the overall latency by replacing the polynomial multiplication module in Crystals?Kyber generated by HLS with a hand-coded Verilog HDL-based number theoretic transform module with high data throughput. The results demonstrate a significant latency improve-ment of approximately 40% compared with the Crystals?Kyber designed solely with HLS, and improved area-time product results.

https://doi.org/10.5573/JSTS.2024.24.3.199

(Dong Wuk Park) ; (Ki Ryun Byeon) ; (Gi Sung Lee) ; (Tae Hee Lim) ; (Kyoung Hwan Jo) ; (Tae Hyoun Oh) ; (Hyung Chul Park) ; (Yun Seong Eo)

In this paper, a 262 MHz NB-IoT RF transceiver IC for Korean M-Bus smart metering service is presented. To mitigate the DC noise and 1/f noise near the narrow signal band and prevent SNR degradation caused by adjacent channel interference, low IF receiver with 4th order poly-phase filter is employed. The prototype is fabricated using the 0.18 μm CMOS process and has a size of 3.3 mm x 3.1 mm. It consumes 41.4/37.8 mW in transmit and receive modes, respectively. The measured results show that the maximum Tx power and OIP3 are +15.4/24 dBm and the receiver sensitivity is -105.4 dBm for PER 10-1 and 50-kbps GFSK modulation with 56 dBc ACR. The measured performance can provide the several-km communication distance for the smart monitoring sensors.

https://doi.org/10.5573/JSTS.2024.24.3.208

(Seoung-Geun Cho) ; (Jin-Ku Kang)

This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery (CDR) circuit with improved jitter tolerance using a shared sampler method. In the proposed design technique, each sampler output is used simultaneously for data decoding and phase detection. Since all samplers are used for phase detection, it has improved jitter tolerance based on high transition density. In this design, the transition density is 0.375. In addition, only four samplers are used per UI, which enables an energy efficient CDR design. Furthermore, the proposed phase detector (PD) minimizes CDR lock point fluctuations by employing pattern-based PD. The receiver with proposed CDR is implemented in a 65-nm CMOS process and has a target of 25 Gb/s data rate. The power consumption of the receiver is 19.6 mW with -7.1 dB channel loss. The energy efficiency of the receiver is 0.784 pJ/bit.

https://doi.org/10.5573/JSTS.2024.24.3.218

(Sungju Ryu)

Digital circuits have been usually evaluated on FPGA for the functional verification before the chip design due to the very expensive fabrication cost. However, SRAM-based processing-in-memory array typically activates multiple wordlines, which is different from the operational principle of the conventional SRAMs. When the evaluation of digital circuits is performed in FPGA, SRAMs are replaced by BRAMs, but it is impossible to change the behavior of the BRAMs, which makes it difficult to verify the analog processing-in-memory concepts using FPGAs. In this paper, we analyze the methods to evaluate the digital SRAM processing-in-memory hardware accelerators on FPGA.

https://doi.org/10.5573/JSTS.2024.24.3.226

(Byung-Kwon An) ; (Xueyong Zhang) ; (Anh Tuan Do) ; (Tony Tae-Hyoung Kim)

Resistive random-access memory (RRAM) is a promising emerging non-volatile memory because it offers high density, low power, low cost, and large R-ratios (RHRS / RLRS). However, the sensing margin of RRAM is significantly degraded because of RRAM resistance variations and R-ratio degradation over usage. To overcome these challenges, this work proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to improve the sensing margin and robustness. The proposed sensing circuit detects a small voltage change through capacitive coupling and adjusts the reference current depending on the cell states (RHRS, RLRS) for sensing margin enhancement. It also reduces sensing delay and energy by up to 53% and 32%, respectively, compared with the conventional CSA. Also, the sensing speed is improved by 2.3?, 2.1?, and 1.9? compared to other current sensing schemes.

https://doi.org/10.5573/JSTS.2024.24.3.240

(Heehun Yang) ; (Jiho Park) ; (Jooseung Lee) ; (Hui-Myoung Oh) ; (Soonwoo Lee) ; (Hoyoung Yoo)

This paper introduces a novel TRNG-PUF structure using Programmable Delay Logic (PDL)-based Ring Oscillators (ROs), offering enhanced performance for both True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUFs). Unlike previous approaches utilizing standard ROs, our design employs PDL to fine-tune the ROs, enabling effective harnessing of entropy for TRNGs and providing unique identification for PUFs. The proposed TRNG-PUF structure is implemented and tested on a Xilinx Artix-7 100T FPGA, demonstrating superior area efficiency and performance. In terms of hardware complexity, it showed the highest hardware efficiency among various designs. Particularly, compared to the conventional structure without shared sources, the proposed TRNG-PUF structure reduces the area of LUT and flip-flops by 41% and 24%, respectively. Moreover, the TRNG component of the structure is evaluated using the NIST SP 800-22 test, and it successfully passed all 15 tests. In contrast, previous TRNG-PUF designs only achieved partial success. Finally, the performance of the PUF is assessed through Hamming distance measurements, which showed excellent HDinter and comparable HDintra values. According to experimental results, the proposed TRNG-PUF structure is not only more area-efficient but also provides improved TRNG and PUF performance compared to previous TRNG-PUF designs.

https://doi.org/10.5573/JSTS.2024.24.3.249

(Yong-Jin Seo)

The double diffused drain N-type MOS (DDDNMOS) transistor with a dipolar source is proposed to realize stable and robust electrostatic discharge (ESD) protection performance. The proposed dipolar source is a structure in which a P+ diffusion layer is intentionally inserted on the side of the N+ source to prevent lateral diffusion of the electron-rich region from the N+ source. According to the 2D simulation and measured TLP results, it was found that the inserted P+ diffusion layer effectively prevented the formation of deep electron channels caused by electron injection. Therefore, the double snapback phenomenon, which is a problem in the conventional DDDNMOS standard device, can be solved.

https://doi.org/10.5573/JSTS.2024.24.3.259

(Gyeong-Pil Jang) ; (Ji-Hun Yang) ; (Su-Young Kim) ; (Young-Bin Chae) ; (Hyuk-Doo Choi) ; (Dae-Gyu Moon) ; (Kyoung-Ho Lee) ; (Chang-Kyo Kim)

Zn0.9Mg0.1O nanoparticles (NPs) were employed as electron transport layers (ETLs) with varying thickness, and the effects thereof on the efficiency of top-emission quantum dot light-emitting diodes (TE-QLEDs) fabricated inside a bank were investigated. Increasing the thickness of the Zn0.9Mg0.1O NP ETL led to reduction in oxygen vacancies, resulting in decreased conductivity and current density of the TE-QLEDs. This reduction in conductivity was confirmed by electron-only device (EOD) characteri-zation. At a Zn0.9Mg0.1O NP ETL thickness of 30 nm, the hydroxide oxygen concentration reached a minimal, minimizing exciton quenching at the quantum dot (QD) and Zn0.9Mg0.1O NP ETL interface and thus enhancing the QD charge balance, significantly improving TE-QLED efficiency. A TE-QLED with a 30-nm-thick Zn0.9Mg0.1O NP ETL exhibited outstanding performance, with a maximum current efficiency of 90.92 cd/A and a top external quantum efficiency of 21.66%. These findings underscore the critical role of Zn0.9Mg0.1O NP ETL thickness in suppressing exciton quenching and optimizing charge balance for enhanced TE-QLED performance.

https://doi.org/10.5573/JSTS.2024.24.3.270

(Naga Ganesh Akuri) ; (Deepak Naik Jatoth) ; (Sandeep Kumar) ; (Hanjung Song) ; (Asutosh Kar)

An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 μW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems.

https://doi.org/10.5573/JSTS.2024.24.3.284

(Chan-Ho Kye) ; (Jihee Kim) ; (Deog-Kyoon Jeong) ; (Min-Seong Choo)

This letter presents a 4.5-to-14 GHz phase-locked loop (PLL)-based clock driver with wide-range 3-shaped LC-VCOs for GDDR6 DRAM test. We use two frequency modes to generate a write clock (WCK) from DC-to-14 GHz. In low-frequency mode under 4.5 GHz, the input from the automatic test equipment (ATE) is bypassed to WCK output. In high-frequency mode, PLL supports high-frequency WCK with good phase noise employing LC-VCOs. We propose 3 LC-VCOs to cover 48 frequency bands which support a frequency range from 4.5-to-14 GHz. Moreover, the current-mode driver with output common mode level control is proposed to provide programmability of the received clock input crossing point for the GDDR6 DRAM test. The prototype chip was fabricated in a 40 nm CMOS technology. The measured frequency tuning range is from 4.5-to-14 GHz with a tuning ratio of 102.7 %. The measured output common mode peak-to-peak difference is 200 mV. The measured integrated RMS jitter is 129 fsrms at 7 GHz, 180 fsrms at 11 GHz, and 365 fsrms at 14 GHz, respectively.