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Probabilistic based CMOS Adder for High Speed Communication Systems

(S. Venkatesh Babu) ; (S. Arumugam)

Power efficient is an important availability for various mobile devices and communication system applications. The proposed probabilistic adder is to trade a lesser amount of accuracy with reduced power dissipation. In this paper, the probabilistic adder is eliminating the some part of the carry propagation path in least significant bit to reduce the power consumption and transistor count. The power consumption and probabilistic error behaviour of the proposed adder is designed and compared with other adders.

Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping

(Young Suh Song) ; (Taejin Jang) ; (Hyun-Min Kim) ; (Jong-Ho Lee) ; (Byung-Gook Park)

In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.

Silicon-controlled Rectifier-based Electrostatic Discharge Protection Circuit with Additional NPN Parasitic Bipolar Junction Transistor for 5-V Application

(Kyoung-Il Do) ; (Yong-Seo Koo)

This paper proposes a novel protection circuit based on a silicon-controlled rectifier (SCR) to prevent electrostatic discharge (ESD) at low voltages. The proposed device consists of an additional NPN parasitic bipolar transistor operated via application of an N+ diffusion region and a well breakdown voltage, to reduce the high trigger voltage caused by the well breakdown voltage of the existing SCR structure. Furthermore, the proposed device exhibits an improved trigger voltage, holding voltage, and dynamic resistance component when compared with existing parasitic PNP bipolar transistors. The proposed ESD protection circuit was manufactured using a 0.18 μm bipolar-CMOS-DMOS; it exhibited a significant improvement in electrical characteristics such as trigger voltage (8.1 V) and holding voltage (3.55 V), according to the results of transmission line pulse measurement. Hence, it is deemed to be suitable for 5-V-class applications.

Handy Calibration Substrate for both Horizontal and Vertical Probing

(Bo Pu) ; (Taeho Kim) ; (Jinho Joo) ; (Wansoo Nah)

This article proposes a novel substrate for a handy SG-GS/SG-SG calibration in both horizontal and vertical probing measurement. The proposed substrate provides two ways of probing for “through” calibration in horizontal and vertical positions without changing the probe holders. It has “through” lines vertically and horizontally using vias and traces, respectively, and both “through” lines were designed to satisfy 50 ohms of characterization impedance. A prototype of the proposed substrate was fabricated using FR4 and then tested in the horizontal calibration resulting in the successful reproduction of all the S-parameters in the horizontal meander test board. It was also tested in the vertical calibration, and was successful to re-produce all the coupling effects in via arrays, demonstrating the effectiveness and handiness of the proposed calibration substrate.

6.5 kV SiC Power Devices with Improved Blocking Characteristics against Process Deviations

(Junki Jung) ; (Ogyun Seok) ; (In Ho Kang) ; (Hyoung Woo Kim) ; (Wook Bahng) ; (Ho-Jun Lee)

Edge termination structures that are insensitive to process deviations were investigated to obtain 6.5 kV SiC power devices with stable blocking characteristics. Edge terminations were designed and verified by a TCAD simulation in consideration of undesirable surface charge states and variation of the implantation window in the termination region. A constant-space floating guard ring (CS-FGR) was sensitive to the variation of the implantation window. A gradually increasing space (GIS) FGR was less sensitive to process deviations than the CS-FGR. We concluded that the GIS-FGR is sufficiently stable for use in high-voltage SiC devices at surface charge densities (Qsurf/q) of 0 to ?1 × 1012 cm?2 and implantation window variations of ?0.3 to +0.3 μm. The optimized GIS-FGR exhibited a high breakdown voltage of over 8 kV at all the Qsurf/q values and in the implantation window variation range considered in this paper.

Body-biasing-based Latch Offset Cancellation Sensing Circuit for Deep Submicrometer STT-MRAM

(Taehui Na)

Even though spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is considered to be a leading candidate for next generation memory, designing a sensing circuit (SC) that achieves sufficient read yield is challenging because of the increased process variation, decreased read current (Iread), and small tunnel magneto-resistance (TMR) ratio. In this paper, a novel body-biasing-based latch offset cancellation SC (BBLOC-SC) that is capable of canceling the offset voltage caused by the latch sense amplifier is proposed. Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed BBLOC-SC achieves a much higher read yield compared to the state-of-the-art SCs, regardless of TMR and Iread.

An Approximate DRAM Design with an Adjustable Refresh Scheme for Low-power Deep Neural Networks

(Duy Thanh Nguyen) ; (Hyun Kim) ; (Hyuk-Jae Lee)

A DRAM device requires periodic refresh operations to preserve data integrity, which incurs significant power consumption. Slowing down the refresh rate can reduce the power consumption; however, it may cause a loss of data stored in a DRAM cell, which affects the correctness of computation. This paper proposes a new memory architecture for deep learning applications, which reduces the refresh power consumption while maintaining accuracy. Utilizing the error-tolerant property of deep learning applications, the proposed memory architecture avoids the accuracy drop caused by data loss by flexibly controlling the refresh operation for different bits, depending on their criticality. For data storage in deep learning applications, the approximate DRAM architecture reorganizes the data so that these data are mapped to different DRAM devices according to their bit significance. Critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop on state-of-the-art deep neural networks.

A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration

(Hwan-Seok Ku) ; (Seungnam Choi) ; (Jae-Yoon Sim)

This paper presents an asynchronous-clocking 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) suitable for high-precision sensor applications. Comparator noise and nonlinearity from capacitor mismatch, as two major performance-limiting problems of SAR ADC, are resolved by noise averaging with a residue integration and a digital-domain capacitor error calibration, respectively. The proposed ADC is implemented using 180-nm CMOS technology in an area of 0.68mm2. The calibration improves SNDR by 5.9 dB and SFDR by 14.3 dB, achieving an SNDR of 87.5 dB and an SFDR of 106.85 dB, respectively.

12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process

(Sanggeun Lee) ; (Taehyoun Oh)

A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 mm2 chip area.

Effects of Ultrasonication on the Electrical Performance of a-IGZO TFTs

(Jae-Yun Lee) ; (Kwan-Jun Heo) ; (Seong-Gon Choi) ; (Jung-Hyuk Koh) ; (Sung-Jin Kim)

In this study, investigate the effect of ultrasonication on the oxide channel layer of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) based on different processing times. The ultrasonication treatment was applied at 40 kHz for 0, 10, 20, and 40 min before post annealing. Ultrasonication improved the electrical and surface morphology properties of a-IGZO thin-film transistors. The a-IGZO TFTs that underwent ultrasonication for 10 min exhibited enhanced electrical performance (saturation mobilities of 11.9 cm2/Vs, current on/off ratio of 3.5 × 107, threshold voltage of 6.1 V, and subthreshold voltage of 0.65 V/dec). Moreover, the dynamic and static responses of a resistive load?type inverter based on a-IGZO with ultrasonication are examined.

Adaptive Non-speculative DFE with Extended Time Constraint for PAM-4 Receiver

(Do-Hyeon Kwon) ; (Hyung-Wook Lee) ; (Kyeong-Min Ko) ; (Taek-Joon An) ; (Jin-Ku Kang)

This paper presents a novel approach to solve the time constraint issue of DFE with PAM4 signaling. By using track and hold operation to sample signals of the same level at two points, the time constraint of 1 UI in direct DFE can be extended to 1.5UI. The FIR-tap employs LVDS structure to maintain common voltage and SS-LMS algorithm is used to obtain the optimal tap weight. The first post-cursor ISI cancellation is done by the LVDS tap and a sufficient settling time is provided by the proposed DFE. The proposed structure may eliminate the loop unrolling speculative DFE for PAM-4, which leads to less hardware for PAM-4 DFE implementation. A PAM-4 serial link using the proposed DFE was designed in a 65nm CMOS technology and analyzed. Channels with 11.9 dB and 13.8 dB losses were compensated through CTLE and the proposed 1 tap DFE, and simulation results demonstrate the time constraint can be extended without deterioration of the eye opening.