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An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration

(Hoyong Jung) ; (Neungin Jeon) ; (Jimin Cheon) ; (Young-Chan Jang)

A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 mm2 and 248 μW, respectively.

A Read Disturbance Tolerant Phase Change Memory System for CNN Inference Workloads

(Hyokeun Lee) ; (Hyuk-Jae Lee) ; (Hyun Kim)

Phase-change memory (PCM) garners attention as the most promising nonvolatile memory (NVM). In particular, PCM is suitable for applications that are not memory intensive, and the convolutional neural network (CNN) inference is widely known as a representative computation- intensive model. Therefore, CNN inference seems to be very suitable for a PCM-based system. However, the PCM suffers from the characteristic of being vulnerable to disturbance errors. In particular, read disturbance error (RDE) becomes a serious problem for workloads involving a large number of zeros, and unfortunately, matrices in CNN are sparse, which inevitably incurs a significant amount of RDEs. In this paper, we present an RDE-tolerant PCM-based system for CNN inference workloads. The proposed method restores vulnerable data words by leveraging a dedicated SRAM-based table. Furthermore, we also propose a replacement policy, which detects non-urgent entries, by utilizing the contents (i.e., counters) in the table. As a result, the proposed method significantly reduces RDEs with minor speed degradation.

A Novel Architecture of Asynchronous Sorting Engine Module for ASIC Design

(Myungchul Yoon)

A novel sorting engine called Sorting Grid (SG) is presented in this paper. SG is intended to be used as a hardware module for ASIC design which can be employed for any ASIC chip requiring fast sorting operation. The SG is implemented by simple modular architecture so that it is easily synthesized with conventional ASIC tools. SG allows inputs with the same key and provides stable sorting for those inputs. SG sorts m-bit N binary inputs in (m+1) cycles with variable cycle time. SG employs a self-timed asynchronous clock of which the period changes according to the operation time of each cycle. The clock period greatly decreases along the cycle. With this clock and a multi-level bypassing scheme, SG has O(N+m) time-complexity for pseudo-random binary inputs. By the simulations with 1.2V-0.13 μm process technology, the sorting rate of the SG is about 1 ns per input for 16-bit inputs.

Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs

(Nosheen Shahzadi) ; (Sanghyeon Baeg)

Traps on Si/SiO2 interface or Si substrate are a big source of variability that cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, causing random fluctuations, variable trap locations are considered on Si/SiO2 interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at five different energy levels (0.35-0.55 eV with a difference of 0.05 eV). The electron charge pumping cycle is recorded to understand each trap's dynamics. In this study, electron charge emission in low time, contributing to substrate current is considered as an indicator to estimate degradation in device performance. The specific value of charge emission in low time contributing to substrate current from an individual-specified trap, reveals the impact of that trap on device degradation. A special case is also discussed to calculate the threshold of failure time based on the accumulation of one femtocoulomb charge in the low time.

Chemoresistive Gas Sensors for Food Quality Monitoring

(Seonyong Lee) ; (Seungsoo Kim) ; (Gi Baek Nam) ; (Tae Hoon Eom) ; (Ho Won Jang)

The maintenance of food quality has become a crucial assignment to obstruct foodborne diseases in the pandemic era. Various methods have been utilized to monitor the freshness of foods, including gas chromatography-mass spectroscopy (GC-MS). However, most of such methods are not suitable for real-time food quality monitoring. Thus, chemoresistive gas sensors have gained high attention for in-situ monitoring of food quality due to their simple structure, small volume, and low price. Herein, we introduce highly efficient food quality monitoring using chemoresistive gas sensors based on metal oxides, metal sulfides, carbon nanomaterials, polymers, and their composites. We provide diverse strategies to improve the detection of food freshness, such as nanostructure construction and heterostructure formation.

Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer

(Eunsang Lee) ; (Jaeduk Han)

This paper presents a 3rd-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1st-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.

Research of Quantized Current Effect with Work Function Variation in Tunnel-field Effect Transistor

(Kang Lee) ; (Sangwan Kim) ; (Garam Kim) ; (Jang Hyun Kim)

In this paper, an investigation has been performed to analyze the relation between on- current (Ion) and gate work function variation (WFV) in the tunnel ?eld-effect transistor (TFET) with help of technology computer-aided design (TCAD) simulation. Comparing the Ion of metal-oxide-semiconductor field-effect transistor (MOSFET) and TFET, it is observed that the quantized current level of TFET is depending on channel bias conditions and width of channel. Therefore, we analyze this current quantization within three categorizations. Firstly, the Ion is quantized by applied level of high gate bias (VGS). At high VGS, the Ion is quantized well following gate WF value near the source-side because the tunnel barrier is made in the specific area by junction between gate and source. However, at low VGS, a lot of current levels are confirmed because almost half of the channel is affected by WFV due to the large tunneling width. Secondly, the quantized Ion variation by WFV is also affected by level of VDS. Because the influence of the channel potential is differed by induced electron density. Finally, the Ion is quantized by width of device. Because, considering metal grain size, the WF value near the source-side is determined only several levels. Then, related with the width, we quantitatively analyzed the quantization of Ion, and based on the probability of WFVs, it is confirmed that the phenomenon of current quantization in TFET is predictable.

An Optoelectronic Transimpedance Amplifier in 180-nm CMOS for Short-range LiDAR Sensors

(Yu Hu) ; (Ji-Eun Joo) ; (Myung-Jae Lee) ; (Sung Min Park)

This paper presents an optoelectronic transimpedance amplifier (OTIA) implemented in a 180-nm CMOS technology, in which a P+/N-well avalanche photodiode (APD) is realized on-chip to reduce signal distortions occurring from bond-wire and I/O pad at the input node, a voltage-mode feedforward input configuration is exploited to boost the transimpedance gain, and a cross-coupled inverter-based post-amplifier (CI-PA) is added to reduce the mismatches from the previous stage. The proposed OTIA demonstrate 95.1-dBΩ transimpedance gain, 608-MHz bandwidth, 4.54-pA/√Hz noise current spectral density, 26.4-dB dynamic range that corresponds to the input currents of 2.38 ?App ~ 50 ?App, and 39.3-mW power dissipation from a single 1.8-V supply. The chip core occupies the area of 0.068 mm2.