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Sensitivity-controllable P-N Diode Temperature Sensor with High-sensitivity

https://doi.org/10.5573/JSTS.2021.21.6.373

(Chun-Hyung Cho) ; (Hyuntai Kim)

A high-sensitive diode temperature sensor using a simple circuit combining a diode and a resistor is proposed. First, a diode voltage-temperature relationship is derived for the temperature change, which is verified through analytical simulations and experimental measurements. In order to enhance the temperature sensitivity, we propose a novel approach that uses the ratio of the resistor voltage to the diode voltage (VR/VD) is employed. We also derive the temperature sensitivity expression of our model as a function of VS (power supply voltage) and VD0 (reference diode voltage measured at 25 oC). It is observed that the temperature sensitivity can be controlled by adjusting Vs. For Vs = 5.0 V, R = 100 Ω, and VD0 = 0.761 V, the temperature sensitivity shows a significant increase by 8.7 times compared to the typical temperature characteristics of the diode over temperatures ranging from -25 oC to 75 oC.

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

https://doi.org/10.5573/JSTS.2021.21.6.381

(Sang Ho Lee) ; (Young Jun Yoon) ; (Jae Hwa Seo) ; (Min Su Cho) ; (Jin Park) ; (Hee Dae An) ; (So Ra Min) ; (Geon Uk Kim) ; (In Man Kang)

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (Vth) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 102 and 104, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

Design and Analysis of DC/DC Boost Converter using Vertical GaN Power Device based on Epitaxially Grown GaN-on-sapphire

https://doi.org/10.5573/JSTS.2021.21.6.390

(Min Su Cho) ; (Sang Ho Lee) ; (Hee Dae An) ; (Jin Park) ; (So Ra Min) ; (Geon Uk Kim) ; (Young Jun Yoon) ; (Jae Hwa Seo) ; (In Man Kang)

In this study, a high-performance vertical gallium nitride (GaN) power transistor was designed by using two-dimensional technology computer-aided design simulator. In addition, the vertical GaN transistor is used to analyze the DC/DC boost converter. Systems requiring high voltages of 1000 V or more, such as electric vehicles, need wide devices to achieve a high breakdown voltage when using conventional power devices. However, vertical GaN transistors can be fabricated with a small device area and a high breakdown voltage. The proposed device has an off-current of 413 pA/cm2, an on-current of 22 kA/cm2, and a high breakdown voltage of 1693 V due to good gate controllability and the undoped-GaN layer. The designed device was used to construct a boost converter that doubled the input voltage and its characteristics were examined. The boost converter produced an output voltage of 1955 V and the voltage conversion efficiency was high at 97.75 %.

Electrical Performances of GaN-based Vertical Trench MOSFETs with Cylindrical and Hexagonal Structure

https://doi.org/10.5573/JSTS.2021.21.6.398

(Geon Uk Kim) ; (Young Jun Yoon) ; (Jae Hwa Seo) ; (Min Su Cho) ; (Sang Ho Lee) ; (Jin Park) ; (Hee Dae An) ; (So Ra Min) ; (In Man Kang)

In this paper, we designed and analyzed the electrical performances of gallium-nitride (GaN)-based vertical trench metal-oxide-semiconductor field-effect-transistors (MOSFETs) using three-dimensional technical computer-aided design (3-D TCAD) simulation. The cylindrical device is generally considered as superior device than the polygonal devices because it has better gate controllability. In the case of GaN-based vertical devices, however, the cylindrical device performs inferiorly to the hexagonal device in terms of crystal directions for the GaN sidewall plane such as m-plane (1-100), a-plane (11-20), and c-plane (0001). The simulation results provide an understanding and design guidelines for which electrical properties of trench FETs are affected by cross-section shape.

Predominance of Carrier Diffusion in Determination of Data Retention in One-transistor Dynamic Random-access Memory

https://doi.org/10.5573/JSTS.2021.21.6.406

(Yi Ju Lee) ; (Seongjae Cho)

One-transistor (1T) dynamic random-access memory (DRAM) has been widely studied for higher array density and obtaining three-dimensional (3-D) array stack viability by truncating the capacitor. However, its rather short retention time has been pointed out as a weak point compared with that of conventional one-transistor one-capacitor (1T1C) DRAM cell. The three dominating factors in determining the data retention in 1T DRAM can be sorted as diffusion, drift, and recombination, by which the programmed carriers are annihilated. In this study, out of those three major factors, the most predominant one is sought in the analytical and mathematical manners. It has been found that carrier diffusion has the key to modulation of the retention time of 1T DRAM and the other two factors are insignificantly small compared with diffusion. Error functions depending on both position and time were adopted to describe the distribution of programmed holes experiencing diffusion and drift in conjunction with solving the continuity equation. It has been concluded that carrier diffusion is the most dominant factor in determining the data retention in 1T DRAM, which suggests that proper ways of decelerating the carrier diffusion out of the channel be sought in optimally designing 1T DRAM cells.

Operation of NO2 Gas Sensors based on Pd-AlGaN/GaN HEMT up to 500 °C

https://doi.org/10.5573/JSTS.2021.21.6.412

(Van Cuong Nguyen) ; (Ho-Young Cha) ; (Hyungtak Kim)

We investigated the performance of NO2 gas sensors based on AlGaN/GaN high electron mobility transistors (HEMTs) at high temperatures up to 500 °C. A 30-nm Pd catalyst layer as the gate of the transistor sensor was deposited by e-beam evaporator for NO2 sensing. At 500 °C, the sensor showed high sensitivity (8.1%), fast response (6 s) and recovery times (7 s) under 1 ppm NO2, thereby proving to be a great candidate for semiconductor sensors under extreme conditions.

A New Coupling Spring Design for MEMS Tuning Fork Structures Demonstrating Robustness to Fabrication Errors and Linear Accelerations

https://doi.org/10.5573/JSTS.2021.21.6.418

(Faisal Iqbal) ; (Hussamud Din) ; (Seung-Oh Han) ; (Byeungleul Lee)

This paper presents a new coupling spring design for the MEMS tuning fork structure. The spring design incorporates the outer arm, inner arm, and torsional arm. The outer and inner arms are connected through the torsional arm to be rotationally symmetric, constituting 180˚ in relation to the center of spring. The designed coupling spring always prioritizes an anti-phase motion providing robustness to linear acceleration. The operation of the spring was validated through FEM simulations and experimental results. The experimental results demonstrated that the anti-phase resonant frequency was 27,280 Hz, whereas the in-phase resonant frequency was 27,780 Hz. Furthermore, the designed coupling spring benefited from a narrow etch cavity and small surface area, making it an ideal design for consumer electronics applications.

A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself

https://doi.org/10.5573/JSTS.2021.21.6.427

(Weizheng Wang) ; (Yan Peng) ; (Zuoting Ning) ; (Peng Liu) ; (Shuo Cai)

Scan-based Design-for-Testability (DfT) methodology has been employed extensively in intellectual property (IP) design to guarantee the testing efficiency. Nevertheless, it also becomes a liability for IP core security because the adversary can steal sensitive information such as secret keys by scan-based attacks. Many protection strategies have been proposed to oppose the scan-based noninvasive attacks by obfuscating the test data. Regrettably, most of these strategies incur the IP performance degradation or put forward the unacceptable resource requirement. In this paper, we propose a new secure scan design scheme, which scramble the test patterns with pseudo-random values and the test responses with selected internal nodes of the circuit. Without the knowledge of circuit design, the adversary cannot apply desired test patterns and cannot recover factual test responses. Thus, it can be prevented to deduce the sensitive information by scan attacks. Through simulation experiments and theoretical analyses, the proposed approach can guarantee the chip security with very low overhead and no impact on the testability.

A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology

https://doi.org/10.5573/JSTS.2021.21.6.438

(Yi Zhang) ; (Xiaopeng Li) ; (Youtao Zhang) ; (Yufeng Guo) ; (Ying Zhang) ; (Hao Gao)

Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

A 70 dB SNDR 10 MS/s 28 nm CMOS Nyquist SAR ADC with Capacitor Mismatch Calibration Reusing Segmented Reference Voltages

https://doi.org/10.5573/JSTS.2021.21.6.449

(Ho-Jin Kim) ; (Jun-Ho Boo) ; (Jae-Hyuk Lee) ; (Jun-Sang Park) ; (Tai-Ji An) ; (Sung-Han Do) ; (Young-Jae Cho) ; (Michael Choi) ; (Gil-Cho Ahn) ; (Seung-Hoon Lee)

This paper proposes a calibrated 14-bit 10 MS/s 28 nm CMOS Nyquist successive-approximation register (SAR) analog-to-digital converter (ADC). The upper 9 bits and the remaining lower 5 bits are determined, respectively, using a binary-weighted capacitor array and segmented reference voltages divided from a simple resistor string. While the proposed calibration is applied only to the critical most significant 4-bit capacitors, the segmented reference voltages to decide the lower 5 bits are reused via a unit capacitor. This creates a small weight on the calibration digital-to-analog converter (DAC) in place of making an adjustment to the small-sized actual capacitor value. The proposed calibration does not require extra capacitors smaller than the unit capacitor, reducing the chip area and circuit complexity. The comparator employs a noise-reduction capacitor, enabling it to realize low-noise performance with low-power. The prototype ADC in a 28 nm CMOS occupies an active die area of 0.062 mm2 and consumes 351 μW at a 1.0 V supply voltage. After calibration, the prototype ADC shows a measured differential non-linearity (DNL) and integral non-linearity (INL) within 1.59 LSB and 2.92 LSB, respectively, at 14 bits with a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 70.0 dB and 85.0 dB at 10 MS/s, respectively.

Novel Process Technologies of a Deep-submicron MOSFET for the High Packing Density of Circuits

https://doi.org/10.5573/JSTS.2021.21.6.459

(Eou-Sik Cho) ; (Sang Jik Kwon)

We have presented some novel process ideas to solve the major challenging problems in submicron device techniques. The key ideas are the ultra-shallow LDD (lightly doped source/drain) junction formation by using the SPD (solid phase diffusion) through ‘amorphous Si / thin oxide’ layer and the Ti silicidation by using selectively etched a-Si layer which is extended over the field oxide region. This TiSi2 layer could be used as a local interconnect with the shrinkage of physical design width of the active mask. Using this FESD (Field Extended Source Drain) technology, the width of the physical active mask could be reduced 2.75 times smaller than that of the conventional structure. We have verified this technology successfully by the fabrication of PMOSFET with 0.76 ?m gate length.

A Reference Clock Doubler with Fully Digital Duty-cycle Error Correction Controller

https://doi.org/10.5573/JSTS.2021.21.6.466

(Dong Gyu Kim) ; (Joon-Mo Yoo) ; (YoungGun Pu) ; (Yeon Jae Jung) ; (Hyung Ki Huh) ; (Seok Kee Kim) ; (Keum Cheol Hwang) ; (Young-Goo Yang) ; (Kang-Yoon Lee)

In this paper, a clock frequency doubler capable of handling large variation in input duty cycle and PVT (Process, Voltage and Temperature) is presented. Clock doubler with XOR gate cannot be used if the duty of the input clock is not 50 %. A circuit that calibrates the duty to 50 % is added in front of the clock doubler, the clock doubler has a low jitter and doubles the frequency even if the duty of the input clock is not 50 %. The fully digital method proposed in this paper overcomes the disadvantages of the existing analog methods, such as standby current and large area due to the use of capacitors and amplifiers, to enable low-current, low-area implementation. The reference clock doubler is implemented using 55-nm CMOS process and the die area is 80 μm x 80 μm. The power consumption is 30 μW under the supply voltage of 1 V. Measured maximum duty cycle error correction range and average frequency error are ±30 % and less than 0.5 %, respectively.

A 320-MS/s 2-b/cycle Second-order Noise-shaping SAR ADC

https://doi.org/10.5573/JSTS.2021.21.6.472

(Jaehyeong Park) ; (Sang-Gyu Park)

A 2nd-order Noise-Shaping ADC using a 2-bit/cycle SAR ADC is proposed. With a designated reference DAC and a signal DAC, three comparators in the SAR ADC enable 2-bit conversion in each comparison cycle. The noise transfer function (NTF) of the ADC is implemented in an error-feedback structure to bypass the need for power-consuming integrator. A low-gain switched input/output open-loop residue amplifier and a switched-capacitor FIR filter realizes the NTF coefficients. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has SNDR of 69.9 dB and power consumption of 4.08 mW, when operated with a sampling rate of 320-MS/s and OSR of 8 achieving a Walden figure-of-merit (FoM) of 39.9-fJ/conv.-step.

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

https://doi.org/10.5573/JSTS.2021.21.6.483

(Prashanthi Metku) ; (Kyung Ki Kim) ; (Yong-Bin Kim) ; (Minsu Choi)

Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models.