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D-RDMALib: InfiniBand-based RDMA Library for Distributed Cluster Applications

https://doi.org/10.5573/JSTS.2023.23.6.341

(Laewon Jeong) ; (Myeong-Seon Gil) ; (Yang-Sae Moon)

RDMA (Remote Direct Memory Access) is a recent communication protocol that allows for the maximum utilization of the performance of InfiniBand, a high-speed network device based on Data Processing Units (DPUs). However, the existing RDMA development method incurs a high implementation complexity, which makes it difficult to apply to a multi-node environment. To solve these problems, we propose D-RDMALib, an efficient and easy-to-use RDMA library suitable for distributed cluster environments. As an effective development tool, D-RDMALib can reduce the implementation difficulty of applying RDMA to distributed multi-node environments. It also improves the accessibility of InfiniBand and RDMA technologies with high entry barriers. In this paper, we demonstrate the efficiency of D-RDMALib by 1) verifying the successful operation of many-to-many communication in distributed nodes, and 2) evaluating the performance by implementing PageRank-based on D-RDMALib. We believe that our work is a novel technique that can be easily applied to existing distributed processing environments as well as to emerging ultra-high-speed in-network technologies such as Quantum InfiniBand.

Time- and Temperature-dependent Degradation of p-GaN Gate HEMTs under Forward Gate Voltage Stress

https://doi.org/10.5573/JSTS.2023.23.6.352

(Myeongsu Chae) ; (Hyungtak Kim)

In this study, we conducted an analysis of time-dependent degradation by applying forward gate bias in AlGaN/GaN high electron mobility transistors (HEMTs) with p-GaN gate. The temperature-dependent breakdown voltage was extracted through step voltage stress with different temperatures. To assess the lifetime of the device, constant voltage stress was performed with varying stress voltages and temperatures. The mean-time-to-failure (MTTF) and activation energy (Ea) was extracted from Weibull plot and Arrhenius plot, respectively. P-GaN gate HEMTs have a negative activation energy and a positive temperature dependence on time-to-failure and breakdown voltage. This temperature dependence suggests that the degradation under forward gate bias is related to hot carriers generated by high electric field in the reverse-biased Schottky junction.

Design of a Vertical Cylinder GaN Junctionless FET based on its GaN-on-GaN Substrate and Electrical Performance

https://doi.org/10.5573/JSTS.2023.23.6.359

(So Ra Jeon) ; (Sang Ho Lee) ; (Jin Park) ; (Ga Eon Kang) ; (Jun Hyeok Heo) ; (Min Seok Kim) ; (Seung Ji Bae,Jeong Woo Hong) ; (In Man Kang)

This study presents a comparative analysis of the vertical cylinder and fin-type junctionless field- effect transistors (JLFETs) based on GaN-on-GaN substrates using three-dimensional technical computer-aided design (3D TCAD) simulations. The on-current (Ion) values of the vertical cylinder and fin-type JLFETs are 6.45 and 5.63 kA/cm2, respectively. The corresponding off-current (Ioff) of the devices is calculated as 2.51 × 10?10¬ and 9.72 × 10?2¬ A/cm2, respectively. Furthermore, their corresponding Ion/Ioff ratios are 2.57 × 1013 and 5.79 × 104, respectively. Additionally, the Ioff ratio of the devices is 2.58 × 109, and the subthreshold swing (SS) is calculated as 101 and 346 mV/dec, respectively. The static resistance (Ron) and breakdown voltage (BV) represent the figure of merits of the power transistor. Herein, Ron of the vertical cylinder-type device is 0.11 μΩ?cm2, which is lower than 0.62 μΩ?cm2 of the vertical fin-type device, whereas their corresponding BVs are calculated as 2,400 and 2,037 V, respectively. These results show that the BV of the vertical cylinder-type device is ~17.8% higher than that of the vertical fin-type device. Therefore, the vertical cylinder-type GaN JLFET has a higher performance than the vertical fin-type GaN JLFET. Herein, we provide guidance in the designing of high-performance vertical GaN power transistors.

A 16 GHz 1-511 Broadband Programmable Frequency Divider

https://doi.org/10.5573/JSTS.2023.23.6.367

(Yang Wang) ; (Yi Zhang) ; (Yufeng Guo)

A high-speed broadband programmable frequency divider chip is designed and implemented in 0.18 μm SiGe BiCMOS process. The chip is based on the 2/3 dual-mode frequency divider, and integrates high-speed logic operation and reset control in the flip-flop to achieve a wide range of continuous integer frequency division ratio. Taking SCFL and CML DFF as basic units, it realizes wide-band operation and obtains a good input sensitivity range. The test results demonstrate that the operating frequency covers 0.1 GHz to 16 GHz. The frequency divider achieves 1-511 continuous frequency division. The output signal phase noise of the 1 GHz input is -153.7 dBc/Hz @ 100 kHz offset in divide-by-8 mode.

A Sound Activity Monitor with 96.3 μs Wake-up Time and 2.5 μW Power Consumption

https://doi.org/10.5573/JSTS.2023.23.6.375

(Jinkee Kim) ; (Yunyoung Jang) ; (Jong Pal Kim)

A novel low power sound activity monitor (SAM) for fast wake-up is presented. SAM is used for low power consumption of intelligent microphones. An intelligent microphone that responds to user voice commands should operate for 24 hours. Normally, the microphone remains in low power mode when there is no external sound input. While the SAM detects external sound input, the SAM changes from low power mode to normal power mode and the microphone remains in normal power mode. The wake-up time from low power mode to normal power mode should be as short as possible so that user commands are not lost. In addition, power mode switching must be prevented from malfunctioning due to artifacts generated when changing between power modes. Low power and wake-up characteristics are improved by simplifying the SAM structure, and the decision logic is designed to be robust against power switching artifacts. The proposed SAM was designed and fabricated based on a CMOS 0.18 μm process, and its features and performance were measured. The SAM operating at 1.8V consumes 2.5 μW power, and the fast wake-up performance of 96.3 μs is measured.

Compact Modeling of a HfO2 Memristor Cell with Dependence on Compliance Current for Large-area Simulations

https://doi.org/10.5573/JSTS.2023.23.6.382

(Saurabh Suredra Joshi) ; (Soomin Kim) ; (Chang-Hyun Kim) ; (Seongjae Cho)

As a next-generation memory, resistive random-access memory (ReRAM) is an emerging memory device owing to its high cell scalability suitable to high-density memory array, data nonvolatility, and high operation speeds. A compact model of an ReRAM with HfO2 as the switching layer material is developed for circuit and system-level simulations in this work. The developed model enables higher level simulation tasks not only for the memory cell operations in the highly packed array and but also for describing the synaptic behaviors in the hardware neuromorphic systems. Inherently dynamic cell operation characteristics and cell-to-cell variability are reflected for more accurate higher-level simulations. The model is validated by the device characteristics experimentally obtained in the existing reports. The representation of multi-level conductance values by controlling the compliance current has been fused into the compact model.

An Analog Front-end Amplifier with Seamless Discrete Time-gain Compensation for Ultrasound Scanner

https://doi.org/10.5573/JSTS.2023.23.6.389

(Min-Hyeong Son) ; (Ji-Yong Um)

This paper proposes an analog front-end (AFE) amplifier with seamless discrete time-gain compensation (TGC) for ultrasound scanners. The AFE amplifier consists of a preamplifier and a programmable gain amplifier (PGA). A real-time TGC operation is typically accomplished with gradual gain increments in PGA. To achieve a seamless gain transition in PGA, this work proposes a preset switching scheme for an initialization of operating points in PGA. In addition, current-reuse operational amplifiers with dynamic push-pull current sources are deployed in the AFE amplifier to further enhance a transient response. The proposed AFE implemented in a 180-nm BCD process occupies 0.19 mm2, and consumes 2.3 mW. The AFE achieves a gain range from 34.3 dB to 50.5 dB with four gain steps, and a transient interval less than 18 ns during a gain transition.

A Single-ring-oscillator based True-random-number-generator with 3-edges Collapse

https://doi.org/10.5573/JSTS.2023.23.6.396

(Eunhwan Kim) ; (Jae-Joon Kim)

This paper presents an all-digital ring oscillator (RO) based true random number generator (TRNG) that harvests entropy as a jitter. The proposed TRNG constructs upon the collapsing RO-based structure and exhibits high immunity against external power attacks. This approach senses the 3-edge collapse point using a single RO without a reference RO, reducing both area and energy consumption. A prototype chip fabricated using 65 nm technology operates between 1.08 V and 1.44 V, occupying an area of 702 ?m2. The randomness of the TRNG passed the NIST randomness test up to 2 LSB when the external power attack was below 300 mVPP. This work demonstrates a throughput of 7.1 Mbits/s at 1.2 V and provides an efficiency of 40.93 Mbit/mJ at 1.08 V.