https://doi.org/10.5573/JSTS.2025.25.1.1

(Hangwook Jeong) ; (Min-Woo Kwon)

Conventional MOSFETs have reached a physical limit with a subthreshold swing of approximately 60 mV/dec at room temperature. To overcome this, various Beyond C-MOS devices are being researched, with the feedback FET (FBFET) attracting attention due to its highly ideal subthreshold swing and high on-current. However, the FBFET operates much more sensitively compared to conventional MOSFETs. Therefore, analyzing the electrical characteristics of the device as its physical parameters are varied is crucial in FBFET research. Despite this importance, research and application of FBFETs have not yet made significant progress, and there is a lack of data analyzing the characteristic changes with parameter variations. In this study, we used a Dual-Gate FBFET to observe changes in electrical characteristics by varying the lengths of the gate and control gate, oxide and body thickness, doping concentration, and the concentration and level of interface traps. An increase in the gate and Control gate lengths led to an increase in threshold voltage, and an increase in oxide thickness also resulted in a higher threshold voltage. An increase in body thickness led to an increase in both on-current and threshold voltage, and an increase in P? and N? doping concentrations resulted in a higher threshold voltage. Additionally, the application of interface traps in the gate and control gate regions increased the threshold voltage. This study’s comparison and analysis of these simulation results confirmed that parameter changes in the gate region critically impact device operation more than changes in the control gate region. This finding highlights the need to pay closer attention to parameter variations in the gate region compared to the control gate during device design and manufacturing processes. We expect that this analysis will significantly aid further research and application of FBFET devices.

https://doi.org/10.5573/JSTS.2025.25.1.9

(Jongho Lim) ; (Myung-Hyun Baek) ; (Min-Woo Kwon)

As the demand for advanced memory technologies grows, the development of next-generation memory devices is required. One promising candidate is resistive random access memory (RRAM), which is advantageous for high-density integration in three-dimensional vertical crossbar array architectures due to its simple metal-insulator-metal structure [1]. In this study, we fabricated an RRAM device and analyzed the characteristics of the HfOx insulating layer when it possesses a nanoporous structure. The HfOx insulating layer was deposited to induce the nanoporous structure by RF sputtering. When the HfOx insulating layer has a nanoporous structure, the device exhibits a minimum current existing at a specific voltage and rectifying properties. These characteristics result from the migration of oxygen vacancies and the presence of oxygen ions in the pores. Depending on the applied voltage magnitude, the internal electric field created by the negatively charged oxygen ions in the pores shifts the voltage point of the minimum current. In addition, the Schottky-like barrier modulation induced by migration of oxygen vacancies leads to a non-linear I-V switching behavior. The resistive switching mechanism observed in the nanoporous insulating layer plays a crucial role in enhancing the device’s performance. These findings provide valuable insights into understanding the electrical characteristics of other RRAM devices with similar structures.

https://doi.org/10.5573/JSTS.2025.25.1.14

(Ji-Ho Park) ; (Jun-Ho Boo) ; (Jae-Geun Lim) ; (Hyoung-Jung Kim) ; (Jae-Hyuk Lee) ; (Seong-Bo Park) ; (Joo-Yeul Yang) ; (Gil-Cho Ahn)

This paper presents a second-order modified feed-forward (FF) delta-sigma modulator for battery management system DC measurement. The proposed ADC employs a modified 3-bit feedback digital-to-analog converter (DAC) with the data weight averaging (DWA) technique to improve the capacitance matching. The modified 3-bit DAC reduces the logic complexity of the DWA by simplifying the switching network of unit capacitors. Additionally, the proposed ADC adopts capacitor swapping technique between the input and reference sampling capacitors to minimize its gain error. To further improve the performance of the proposed ADC, system-level lowfrequency chopping (CHL) and correlated double sampling (CDS) are employed to mitigate offset and flicker noise. The prototype ADC is fabricated in a 180 nm CMOS process, and the core area is 0.53 mm2 . It consumes 9.48 μW from a 1.8 V supply voltage at an operating clock frequency of 19.2 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 102.4 dB, a resolution of 7 μVrms, and an offset of 6.86 μV, resulting in a Schreier figure-of-merit (FoM) of 165.3 dB.

https://doi.org/10.5573/JSTS.2025.25.1.21

(So Ra Jeon) ; (Sang Ho Lee) ; (Jin Park) ; (Min Seok Kim) ; (Seung Ji Bae) ; (Jeong Woo Hong) ; (Won Suk Koh) ; (Gang San Yun) ; (In Man Kang) ; (Young Jun Yoon)

In this study, we conducted an irradiation experiment using protons with 5 MeV energy and a fluence of 5 ×1013 cm?2 to analyze the effects on AlGaN/GaN high electron-mobility transistors (HEMTs). After proton irradiation, the on-resistance (Ron) value increased by 57%, the on-state current (Ion) decreased by 26.78%, and the off-state current (Ioff) increased by 89.63%. Despite these changes in Ion and Ioff, there was no significant change in the threshold voltage (Vt). This indicates that the two-dimensional electronic gas (2DEG) density, which determines Vt did not sustain significant damage. The degradation in device characteristics was attributed to other factors, which were analyzed through a resistance-based equation. Additionally, we performed simulation fitting to complete a quantitative cause analysis. We believe that our findings will contribute to preliminary verification research for high-reliability experiments, such as space and aviation semiconductors.

https://doi.org/10.5573/JSTS.2025.25.1.30

(Xinfeng Zheng) ; (Weifeng Lu) ; (Yubin Wang) ; (Shuaiwei Zhao) ; (Honglei Huo)

In this paper, to improve the performance of L-shaped gate heterojunction tunneling field-effect transistor (LG-HJ-TFET), an L-shaped gate negative capacitance Si/Ge heterojunction TFET with channel doping (NCHJCD-LTFET) was proposed, whose electrical characteristics were investigated through technology computer-aided design simulations in Sentaurus. The NCHJ-CD-LTFET has doping (n+-doping for an n-type TFET) in the corner region of the channel, which plays an important role in modulating the energy bands that reduce the bandgap between the source and channel in the doping area. Thus, compared with the LG-HJ-TFET, the band-to-band tunneling of NCHJ-CD-LTFET occurs at a lower gate voltage (VGS), and the threshold voltage (VTH) is significantly reduced from 0.221 to 0.181 V. In addition, a ferroelectric layer was deposited above the horizontal gate dielectric to further improve the electrical characteristics owing to the negative-capacitance effects. With comprehensive adjustment the doping concentration of the channel corner region (NCH,CO) and the thickness of the ferroelectric layer (TFE), the NCHJ-CD-LTFET had a low VTH of 0.145 V, a high on-state current (ION) of 27.5 μA/μm, a high switching current ratio (ION/IOFF) of 2.1×108 and a steep average subthreshold slope (SSAVE) of 24.92 mV/decade.

https://doi.org/10.5573/JSTS.2025.25.1.41

(Junhyeong Ji) ; (Jonghee Park) ; (Jiseok Lee) ; (Hwarang Baek) ; (Youbean Kim)

The device power supply (DPS) utilized in automated test equipment (ATE) for semiconductor testing is responsible for applying and measuring voltage/current to the device under test (DUT). The choice of DPS in ATE can vary based on the equipment’s purpose, specifications, and the targeted DUT for measurement. Consequently, the efficiency of equipment development has been compromised due to different evaluation environments dictated by various DPS manufacturers. This paper addresses this challenge by proposing the establishment of a universally applicable evaluation environment for equipment development, independent of the operational specifications of DPS, leveraging field programmable gate arrays (FPGA). In this study, we initially design and validate an FPGAbased SPI communication module aligned with the specifications of Analog Devices’ AD5560, commonly applied in mass-produced semiconductor test equipment. Based on these results, we present a universal DPS evaluation environment that can be adapted to various DPS development scenarios.

https://doi.org/10.5573/JSTS.2025.25.1.50

(Joon-Kyu Han)

A reliable oscillatory neural network (ONN) is demonstrated using a thermally stable single transistorbased oscillator (1T-oscillator). Instead of relying on thermally sensitive impact ionization (I.I.), thermally insensitive band-to-band tunneling (BTBT) is utilized to trigger a single-transistor latch (STL), ensuring stable oscillation characteristics. The study investigates the properties of coupled oscillators, the fundamental elements of ONN, across different temperature settings to confirm thermal stability effects. Additionally, the reliability of ONN is verified through a vertex coloring task, a representative problem in nondeterministic polynomial time hard (NP-hard) combinatorial optimization.

https://doi.org/10.5573/JSTS.2025.25.1.56

(Dasom Ahn) ; (Seongmin Ahn) ; (Taehui Na)

In the era of rapidly increasing data volume, complementary metal-oxide-semiconductor-based von Neumann structures have encountered several limitations, such as increased leakage current and data movement overhead. To solve this problem, computing-in-memory (CIM) that performs simple operations in memory has emerged. In this paper, we propose an area optimized CIM platform based on spin-transfer torque magnetic random access memory (STT-MRAM). Compared with previous CIM, the proposed CIM platform is area optimized by performing AND/OR logic functions using fewer reference word lines, and it uses an offset-canceling current-sampling sense amplifier to provide more reliable operation. Monte Carlo HSPICE simulation results based on industry-compatible 28-nm model parameters demonstrate the functionality and performance of the proposed CIM platform.

https://doi.org/10.5573/JSTS.2025.25.1.66

(Seongil Yeo) ; (Jaejin Kim) ; (Gunmo Koo) ; (Kunhee Cho)

The cascode current mirror is the most widely used block in analog circuit design, and wide voltage swing operation is essential for low-supply voltage applications. In wide dynamic-range applications, such as current sensing in DC-DC converters, the current mirror must maintain high accuracy across a wide range of reference currents while enabling wide voltage swing operation at the maximum reference current. In this paper, a wideswing self-biased cascode current mirror for wide dynamic-range applications is described. Unlike conventional structures, the proposed design is biased by a non-isolated active device without using an extra current path or an isolated active device. The proposed current mirror demonstrates higher accuracy for a wide-range of reference currents compared to prior wide-swing cascode current mirror designs and offers a more compact design.

https://doi.org/10.5573/JSTS.2025.25.1.71

(Yanning Chen) ; (Dongyan Zhao) ; (Fang Liu) ; (Yang Zhao) ; (Zhen Fu) ; (Yali Shao) ; (Dong Zhang) ; (Yucheng Pan) ; (Xiangyu Meng)

The layout of matching devices is crucial in analog circuit design as it impacts matching, parasitic effects, and performance. Common-centroid layout, a popular method, minimizes mismatches but designing an efficient algorithm is challenging. This paper introduces a comprehensive automated matching placement algorithm for analog circuits, optimizing both common-centroid requirements and device positions to enhance accuracy and minimize area. Under the premise of minimizing performance degradation, we implemented a fully automated process from netlist to final design, demonstrating effective matching placement for transistor arrays in differential pairs and current mirrors, significantly reducing layout area and parasitic effects.

https://doi.org/10.5573/JSTS.2025.25.1.82

(KwonWoo Kang) ; (SoYoung Kim)

An automatic methodology is proposed to optimize analog device placement using reinforcement learning (RL). Device characteristics are influenced by local layout effects and the process node used; hence, physical layout information from post-layout simulation acts as the input for an artificial neural network (ANN). Trained ANNs can be implemented as surrogate models for length of diffusion and deep trench isolation, which are integrated into the reward functions of the learning agent. The Q-learning method is employed for RL. The proposed method emulates design expert expertise by sequentially applying multiple Q-learning with selected reward functions. This approach effectively completes local layout effect-aware automated placement in the early setup stage of advanced process nodes, even with limited design knowledge. Finally, two fundamental analog circuits, the folded cascode operational transconductance amplifier and comparator, are employed to demonstrate the method’s ability to achieve zero threshold voltage variation under local layout effects using dummy transistors and guard rings while maintaining area efficiency

https://doi.org/10.5573/JSTS.2025.25.1.94

(Ibrar Ali Wahla) ; (Muhammad Abrar Akram) ; (In-Chul Hwang)

In this brief, a fully-integrated output-capacitorless digital low-dropout regulator (DLDO) is proposed utilizing the parallel proportional and integral (PI) controllers to achieve reduced voltage undershoot (?VREG) and fast transient response time (TREC). The proposed PI controllers are implemented with the self-shifting bidirectional shift registers (SS-SRs) in coarse-fine dual loops along with complimentary PMOS and NMOS power transistors in coarse switch array and small-sized PMOS only transistors in fine switch array. Complimentary connections of PMOS and NMOS power transistors compensate for the load current (ILOAD) to reduce the ?VREG, and smallsized PMOS reduces the steady-state voltage ripples. The proposed DLDO was designed and fabricated in a 65-nm CMOS process with an active area of 0.08 mm2 . Simulated results demonstrate that the proposed capacitor-less DLDO operates with an input voltage range of 0.7 V-1.2 V. For a load current step of 460 mA at VDD = 1.2 V, the proposed DLDO recovers a ?VREG of 74 mV within 8 ns achieving an efficient load regulation of 0.004 mV/mA with a peak current efficiency of 99.58 %.

https://doi.org/10.5573/JSTS.2025.25.1.102

(Junyoung Choi) ; (Suin Jang) ; (Dongmyeong Lee) ; (Sukkyung Kang) ; (Sanha Kim) ; (Sarah Eunkyung Kim)

To enhance the density and performance of semiconductor devices, 3D packaging with hybrid Cu bonding is emerging as a critical technology. One of the dielectrics used in hybrid Cu bonding is SiCN, typically deposited using PECVD (plasma-enhanced chemical vapor deposition). In this study, we investigated SiCN deposited at room temperature using PVD (physical vapor deposition). The SiCN, with a thickness of 150 nm, exhibited a surface roughness of 0.3-0.4 nm after the CMP (chemical mechanical polishing) process and a contact angle of about 10 degrees and dielectric constant of 3.9, indicating its potential as a dielectric for hybrid Cu bonding. And, PVD SiCN-SiCN bonding was performed at 260?C, resulting in a uniform and void-free interface.