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Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

(Chaewon Yun) ; (Sangwan Kim) ; (Seongjae Cho) ; (Il Hwan Cho) ; (Hyunwoo Kim) ; (Jang Hyun Kim) ; (Garam Kim)

In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.

Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

(Moonjeong Choi) ; (Juhwan Park) ; (Seoungyeol Choi) ; (Kyungbae Kwon) ; (Yeji Lee) ; (Wonyeong Jang) ; (Jongwook Jeon)

In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP.

Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations

(Min-Ki Ko) ; (Jang Hyun Kim) ; (Garam Kim)

The electrical characteristics of line tunneling field-effect transistor (LTFET) is analyzed by technology computer-aided design (TCAD) simulation when the material and doping concentration at the end of the source junction are changed. Partial use of SiGe at the end of Ge source can reduce power consumption by reducing off-state current (IOFF) while maintaining on-state current (ION). In addition, if the doping concentration at the end of the source is lowered, ION is improved and electrical characteristics suitable for high performance applications can be obtained. But these two methods also have disadvantages. In the case of lowering doping concentration at the end of the source, IOFF is higher than conventional LTFET. In the case of Partial use of SiGe at the end of Ge source, ION is lower than conventional LTFET. However, combining these two methods can overcome each other’s disadvantages with the advantages of the other method.

Reduction of the Pass Gate Effect with a Spherical Shallow Trench Isolation in the BCAT Structure

(Yeon-Seok Kim) ; (Chang-Young Lim) ; (Min-Woo Kwon)

We investigates the pass gate effect, a type of adjacent cell interference, through TCAD simulations of a typical DRAM structure at the 1y-nm technology node. Our results show that the pass gate effect is highly dependent on several factors, including the geometrical distance, the ratio between oxide and active silicon, and the oxide trap density at shallow trench isolation. To explain the pass gate effect, we used energy band diagrams and analyzed its tendencies in various environments. Based on our analysis results, we propose and optimize a spherical shallow trench isolation structure. Our analysis results convincingly demonstrate that the proposed structure is effective in mitigating the pass gate effect compared to typical structures.

A Lightweight Scan Architecture against the Scan-based Side-channel Attack

(Xiangqi Wang) ; (Xingxing Gong) ; (Xianmin Pan) ; (Weizheng Wang)

The demand for cryptographic chips is growing rapidly in the market nowadays. Chips must undergo rigorous testing in order to promote quality. Scan-based design for testability (DFT) is widely used to improve the quality of testing. However, scan chain technology also provides illegal users with convenience. They can steal sensitive information of circuit under test (CUT) during testing, which seriously threatens the security of IP cores. Currently, researchers have proposed many secure strategies, but most of them affect the test quality or cause larger hardware overhead. In this paper, we propose a lightweight scan architecture against the scan-based side-channel attack. In this method, a number of logic gates, a linear feedback shift register (LFSR) and two corresponding counters are integrated into the design in order to ensure the security of the design. The normal scan operation can be performed only if users enter the correct scan input key at the K clock cycles. Otherwise, the scheme will incur scan obfuscation. Therefore, illegal users can only observe some incorrect responses from the scan output port. It is known from simulation results and theoretical analysis that the scheme is able to successfully defend against the scan-based side-channel attack while having extremely low overhead and high testability.