https://doi.org/10.5573/JSTS.2024.24.4.289

(Sung-Won Lim) ; (Dong-Woo Jee)

A wide operating range, fast settling, and accurate current sourcing LED driver for PPG (Photoplethysmography) sensor applications is presented. Proposed NMOS resistor array and RC-time constant based calibration circuit precisely control target LED driving current with less than 0.5% error over process variations. For the fast settling of pulse-width modulation (PWM) based boost converter loop, pulse-width prediction technique is proposed which greatly improves the settling time. The driver circuit is designed in 180-nm CMOS process, supporting green/red/infrared LED driving voltage, 0.1-100% duty-cycling and 1-100 mA driving current.

https://doi.org/10.5573/JSTS.2024.24.4.296

(Seokwon Lee) ; (Yonghwan Lee) ; (Chanhee Cho) ; (Kuduck Kwon)

In this paper, a CMOS nonmagnetic circulator and band-selection balun-low noise amplifier (LNA) with RF time-domain self-interference cancellation (SIC) are presented to realize an advanced in-band full-duplex (IBFD) transceiver. The capacitor (C)-inductor (L)-C nonmagnetic circulator based on an N-path filter and time-domain RF SIC with multi delay tap are employed to achieve low receiver (RX) and transmitter (TX) insertion losses and high SIC. Because the circulator does not possess out-of-band (OB) blocker rejection capability, the band-selection N-path balun-LNA is proposed to replace the functionality of the OB blocker rejection of the conventional SAW filters. Simulated in a 65 nm CMOS process, the circulator and balun-LNA with RF canceller achieved a noise figure of 6.6 dB, voltage gain of 17 dB, and SIC of 58 dB. It has an active die area of 1.61 mm2, and consumed 14 mA for a nominal supply voltage of 1 V.

https://doi.org/10.5573/JSTS.2024.24.4.305

(Sungyoun Hwang) ; (Hyelin Seok) ; (Yongtae Kim)

This paper introduces a novel and efficient approximate 4-2 compressor and multipliers that significantly improve overall computation accuracy with marginal hardware overhead. The proposed compressor incorporates an error recovery logic to rectify output errors under specific input conditions. As a result, the proposed multipliers, featuring this error recovery compressor, exhibit substantial improvements in normalized mean error distance (NMED) and mean relative error distance (MRED) by up to 89.8% and 97.1%, respectively, compared to existing approximate multipliers considered in this paper. Furthermore, when implemented in a 32-nm CMOS technology, the proposed designs enable noteworthy reductions of up to 25.2%, 22.9%, and 23.4% in area, power, and energy, respectively, in comparison to the alternative designs. The effectiveness of the proposed design is further validated through its application in a digital image processing algorithm.

https://doi.org/10.5573/JSTS.2024.24.4.316

(Sieun Lee) ; (Yunyoung Jang) ; (Jong Pal Kim)

A tilted plate electrostatic actuator (TPEA) capable of producing large electrostatic forces is proposed. TPEA consists of an inclined top plate with one edge touching the floor, a torsional spring that holds the top plate to the structure, and a bottom electrode. As a result of theoretical and simulation analysis, TPEA has an electrostatic force that is 6.5 times and 22.8 times greater than the existing parallel plate actuator and vertical comb actuator, respectively. Specifically, the electrostatic force per unit area is 195 N for a vertical comb actuator, 731 N for a parallel plate actuator, and 4.7 kN for TPEA. TPEA can generate the same electrostatic force with only 21% of the applied voltage compared to the vertical comb actuator. Specifically, a voltage of 50 V must be applied to generate a force of 195 N in a vertical comb actuator, whereas a voltage of 10.5 V only needs to be applied in TPEA.

https://doi.org/10.5573/JSTS.2024.24.4.323

(Min Suk Song) ; (Hwiho Hwang) ; (Junsu Yu) ; (Sungmin Hwang) ; (Hyungjin Kim)

Flash memory is gaining attention due to its scalability, high reliability, and multilevel capabilities. This study investigated the charge trapping characteristics of high permittivity HfO2 films with Al2O3 as a blocking oxide. TAHOS (TiN-Al2O3-HfO2-SiO2-Si) structure capacitors were fabricated to explore the annealing effects for charge trap flash (CTF) memory device applications. HfO2, serving as a charge trapping layer, offers the advantage of achieving a wide memory window owing to its high trap density. In this work, various characteristics related to memory cells were examined based on annealing temperature and gas type. Post-deposition annealing (PDA) was conducted from 900 °C to 1050 °C and forming gas annealing (FGA) was performed at 450 °C for 10 minutes using H2 gas. We analyzed the memory window and flat-band voltage distributions by measuring C-V characteristics. These results suggest that optimal annealing conditions can be helpful to improve memory characteristics in TAHOS stacked flash memories.

https://doi.org/10.5573/JSTS.2024.24.4.332

(Sung-Hyun Park) ; (Sang-Gyu Park)

This paper presents a third-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter and mismatch shaping for capacitive digital-to-analog converters (CDACs). To achieve third-order noise shaping, the error feedback (EF) structure and cascade of integrators with feed-forwards (CIFF) structure were cascaded. The amplifier used in EF and CIFF is a V-T-V converter which is insensitive to PVT variation. To implement mismatch shaping, one more CDAC is used to generate residue voltage with data-weighted averaging. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has signal-to-noise and distortion ratio (SNDR) of 82.7 dB and power consumption of 435 μW, when operated with a sampling rate of 40-MS/s and over-sampling ratio of 10, resulting in a Schreier figure-of-merit (FoM) of 179.4 dB.

https://doi.org/10.5573/JSTS.2024.24.4.343

(Byeongkwan Jin) ; (Mookyoung Yoo) ; (Sanggyun Kang) ; (Hyeoktae Son) ; (Kyounghwan Kim) ; (Jihyang Wi) ; (Gibae Nam) ; (Hyoungho Ko)

This paper proposes a second-order delta-sigma modulator based on a differential difference amplifier without an input buffer. We introduce a delta-sigma modulator in this study with a structure that eliminates the need for an input buffer, thereby effectively mitigating the area and power consumption issues inherent in existing delta-sigma modulators employing an input buffer. The proposed circuit comprises two integrators for forming a loop filter, a comparator serving as a quantizer, and additional sub-blocks. Fabrication of the proposed circuit is carried out using the TSMC 0.18-μm RFCMOS process, resulting in an active area of 0.56 mm². The application of a differential difference amplifier input stage in this paper achieves a high-input impedance, consequently reducing the extra area and power consumption associated with the drawbacks of an input buffer. The signal-to-noise ratio (SNR) of the proposed circuit attains a maximum level of 76 dB, and the effective number of bits (ENOB) is 12.3 bits.

https://doi.org/10.5573/JSTS.2024.24.4.355

(Eunsang Lee) ; (Sanghun Lee) ; (Changhyun Pyo) ; (Hyunseok Kim) ; (Jaeduk Han)

This paper presents a 2-GS/s 6-bit single-channel speculative loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with comparator offset calibration. The proposed loop-unrolled SAR ADC speeds up its conversion speed by selecting one of the pre-determined capacitive digital-to-analog converters (CDACs) speculatively. A foreground comparator offset calibration for the speculative loop-unrolled SAR ADC is introduced to improve the ADC performance by reducing the input parasitic capacitance and minimizing the logic fan-out in comparator internal clock path. The CDAC switching method that minimizes the variation of the output common-mode (CM) voltage is applied to be compatible with the proposed foreground comparator offset calibration. In addition, the modified double-tail comparator structure is adopted for reducing the kickback noise without the speed overhead. The proposed SAR ADC achieves a 2-GS/s sampling rate with only a single-channel without a time-interleaving technique. The ADC is fabricated in 28-nm CMOS and has a 33.1-dB SNDR at a low input frequency and a 29.9-dB SNDR at the Nyquist frequency with a 6.2-mW power consumption from 1.2-V supply voltage.

https://doi.org/10.5573/JSTS.2024.24.4.365

(Gyeong Jae Lee) ; (Yoon Jun Kwon) ; (Young Suh Song) ; (Hyunwoo Kim) ; (Jang Hyun Kim)

In this paper, we investigated the optimization of the fin width and height with an effective width of 40 nm under the conditions considering self-heating effect (SHE) through TCAD simulation. To ensure the reliability, calibration is performed with transfer curves based on experimental data. We demonstrate the region of device characteristic inversion caused by the difference in thermal resistance based on the variation in the area of heat dissipation for various fin widths. As a result, it is found that a fin width of 10 nm, which is neither too narrow nor too wide, is less affected by SHE.

https://doi.org/10.5573/JSTS.2024.24.4.373

(Hak Jun Ban) ; (Seung Won Lee) ; (Wan-Sik Hwang) ; (Seul Ki Hong)

This study proposes sensor components that can be created using temperature-restricted processes, considering a monolithic 3D system structure for the configuration of next-generation intelligent semiconductor systems. We developed a UV-C detecting sensor using and successfully demonstrated its functionality. Unlike conventional-methods that relied on high voltage and intense UV-C radiation for sensing, our research proved that sensing is achievable with significantly lower voltage and intensity. These innovative results are not limited to advanced packaging and sensor fields but can also be applied across various research areas within the semiconductor industry. Furthermore, the flexible manufacturing approach presented in this study holds great potential not only for industrial applications but also for experimentation and research in academia and research institutions. Therefore, the outcomes of this study are anticipated to drive innovative advancements in the semiconductor industry and have a significant societal and economic impact through their applicationacross diverse fields.

https://doi.org/10.5573/JSTS.2024.24.4.379

(Yeong-Gil Kim) ; (Chae-Eun Oh) ; (Ye-Lim Han) ; (Dong-Ho Lee) ; (Joon-Young Lee) ; (Kyoung-Seok Son) ; (Jun Hyung Lim) ; (Ick-Joon Park) ; (Sang-Hun Song) ; (Hyuck-In Kwon)

We demonstrated that the indium composition ratio in the channel layer significantly affects the electrical stability of top-gate self-aligned (TG SA) coplanar structure indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) under self-heating stress (SHS) conditions. The transfer curves of the In-poor IGZO TFT continuously shifted in the positive direction with extended stress time, without a significant change in the subthreshold swing (SS) and field-effect mobility (μFE) values during SHS application. In contrast, the transfer curve of the In-rich IGZO TFT shifted in the negative direction until the SHS time reaches 1200 s, after which it shifted in the positive direction with extended stress time. Besides, SS and μFE values continuously increased as the SHS time increased in the In-rich IGZO TFTs. The unusual behavior of the TG SA coplanar In-rich IGZO TFT during SHS is mainly attributed to the more pronounced diffusion of hydrogen (H) atoms from the n+-IGZO source/drain extension region to the IGZO channel region in the In-rich IGZO than in the In-poor IGZO. The H atoms diffused into the IGZO channel layer act as either shallow donors or deep acceptors, depending on their concentration and environmental conditions, thus causing the abnormal behavior of IGZO TFTs during SHS.

https://doi.org/10.5573/JSTS.2024.24.4.387

(Jaewoo Lee) ; (Yungjun Kim) ; (Yoocheol Shin) ; (Seongjo Park) ; (Hojong Kang) ; (Daewoong Kang) ; (Myounggon Kang)

This study presents an in-depth investigation of the channel profile and program speed of non-ideal vertical 3-dimensional (3D) NAND Flash Memory. Using 3D technology computer-aided design (TCAD) simulations, the channel profiles were transformed into oxide-nitride-oxide (O/N/O) structures, providing insights into their impact on the device performance. Step-by-step programming was conducted for the initial state of each channel profile. Upon applying the programmed voltage, variations in the E-field of the tunneling oxide were observed based on the channel profile. Consequently, the concentration of the trapped electrons in the nitride, depending on the channel profile, was identified. Therefore, this study analyzed the influence of E-field differences due to channel profiles on the program speed and investigated vulnerable structures.