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Insight into the Charging and Relaxation Dynamics of Diffusive Memristors in Integration-and-fire Neuron Applications

https://doi.org/10.5573/JSTS.2022.22.6.387

(Ju Hwan Park) ; (Won Hee Jeong) ; (Byung Joon Choi)

Artificial neural networks (ANNs) have been studied to mimic biological neurons because of the limitations of conventional computing. Among various ANNs, the spike neural network (SNN) is advantageous owing to its energy efficiency. To demonstrate the effectiveness of the SNN, circuits of integrate-and-fire (IF), leaky IF (LIF), and Hodgkin-Huxley model have been studied using various methods. These circuits contain an external capacitor to mimic membrane behavior. In this study, it is expected that the LIF circuits can be simplified by adopting a diffusive memristor made of Pt/Ag-doped HfOx/Pt. Volatile threshold switching was observed and modeled by performing electrical measurements. Their capacitive properties and relaxation behavior were interpreted by the internal capacitor and dissolution of the conducting filament. Pulse trains were adjusted to confirm the possibility of implementing an LIF neuron without an external capacitor.

Design of a Packaged Multi-radius Multi-path Solenoidal Inductor for Redistribution Layers

https://doi.org/10.5573/JSTS.2022.22.6.395

(GiWon Kim) ; (SoYoung Kim)

This paper proposes a three-dimensional solenoidal inductor using a “multi-radius multi-path” (MRMP) structure that targets integrated voltage regulators (IVRs). Multi-radius (MR) refers to the inclusion of additional turns inside the solenoid, and multi-path (MP) describes the division of a single metal into two paths to reduce non-uniformity in currents due to differences in length. Using an MRMP structure, we propose two new inductor designs for fan-out wafer-level packaging. A two-layer MRMP approach that implements the multi-path in an additional layer, and a one-layer MRMP configuration avoids the need for an additional layer by incorporating the multi-path in an inner turn. We compare inductance and quality performance according to the frequency of the two designs. When the MR technique is applied, the inductance increases due to the increase in the length of the inductor, but resistance also increases. As the frequency increases, alternating current (AC) resistance becomes dominant. The MP increases the quality factor by alleviating skin and proximity effects, which are the main causes of increased AC resistance. Analytical modeling is carried to rapidly estimate and optimize direct current inductance using partial inductance. To verify the improvement in efficiency due to the proposed inductor structure, we propose a prototype IVR that includes inductor loss and investigate the efficiency with circuit simulations using an IVR design with a conversion ratio of 3.6 V:1.8 V operating at 10 MHz. By using the two-layer MRMP inductor, the prototype IVR efficiency increases from 72.6% to 82.1%. A one-layer MRMP inductor, an IVR design with conversion ratio of 1.8 V:1.0 V and an operating frequency of 40 MHz, increases the maximum efficiency from 56.6% to 75.1%.

Small-signal Modeling of InP HBT based on PSO-ELM Neural Network

https://doi.org/10.5573/JSTS.2022.22.6.407

(Jincan Zhang) ; (Yunhang Fan) ; (Min Liu) ; (Jinchan Wang) ; (Liwen Zhang)

Extreme Learning Machine (ELM) is a new learning algorithm for single-hidden layer feedforward neural network, which has been widely used in lots of fields. However, it still has the insufficiency of randomly determining the hidden layer threshold and output weight, which leads to ill-conditioned output. In order to avoid the risk of decreasing prediction accuracy caused by this possibility, the ELM is optimized using particle swarm algorithm. A Particle Swarm Optimization (PSO) enhanced ELM algorithm is proposed to accurately model the small-signal properties of InP Heterojunction Bipolar Transistors (HBTs). PSO-ELM algorithm solves the problem of unstable prediction data caused by random determination of input weights in ELM. Comparing the modeling effects of the PSO-ELM model and the ELM model under different bias conditions for a 1 μm×15 μm InP HBT, it is proved that the PSO-ELM algorithm has better consistency with the measured data.

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiOx Buffer Layer for RRAM Passive Crossbar Array

https://doi.org/10.5573/JSTS.2022.22.6.417

(Tae-Hyeon Kim) ; (Sungjoon Kim) ; (Kyungho Hong) ; (Hyungjin Kim) ; (Byung-Gook Park)

As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al2O3/ TiOx/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOx encompassing metallic and semiconducting properties; and three devices with different TiOx were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiO1.74 sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 27 × 27 array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

A CMOS Dual-mode DC-DC Converter with a Digital Dual-mode Controller

https://doi.org/10.5573/JSTS.2022.22.6.426

(Jong Whan Lee); (Kwang Sub Yoon)

This paper describes a CMOS dual-mode DC-DC converter with a digital mode controller, which includes PFM controller and PWM controller. The proposed dual mode controller employs 3-bit control circuit to select a number of counts from a 5-bit digital counter, so that the 3-bit control circuit is capable of adjusting the transient boundary load current between PFM mode and PWM mode. The proposed dual-mode DC-DC converter with a digital dual-mode controller was implemented with a 180 nm 1P/6M BCDMOS process. The measurement results demonstrated the wide range of the input voltage from 2.2 V to 5.0 V with a fixed output voltage of 1.2 V with 3-bit digital capability to control boundary current between PFM mode and PWM mode. The proposed DC-DC converter achieved the peak PFM and PWM power efficiencies of 85% and 91 %, respectively, with an output ripple voltage of 12 – 32 mV at a switching frequency range of 60 kHz to 2.3 MHz and a load current range of 10 mA to 500 mA.

A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs

https://doi.org/10.5573/JSTS.2022.22.6.436

(Kiho Seong) ; (Jae-Soub Han) ; (Sung-Eun Kim) ; (Yong Shim) ; (Kwang-Hyun Baek)

Noise-shaping successive-approximation-register (NS-SAR) ADCs have become one of the most promising candidates for high-resolution data converters over the past decade. This is due to the fact that they combine the advantages of delta-sigma modulation and SAR ADCs. In this hybrid architecture, the quantizer and residue feedback DAC can be replaced by SAR, a replacement which achieves high SNR while also benefiting from superior power efficiency and low cost. For NS-SAR ADCs, various implementations of loop filters for residue processing exist that can realize the noise transfer function (NTF) for NS effects. In addition, many noise reduction techniques have been proposed that suppress additional noises not shaped by NTF. This paper describes the basics of NS-SAR ADCs while also reviewing noise reduction techniques, which include the implementation of a loop filter for residue handling, kT/C noise rejection, and capacitive DAC mismatch error shaping. It also outlines advanced architectures that can overcome the limitations of NS-SAR ADCs.

Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL

https://doi.org/10.5573/JSTS.2022.22.6.452

(Chang Young Lim) ; (Min-Woo Kwon)

In this article, we evaluate gate induced drain leakage that affects the refresh time of buried cell array transistor DRAM cells. We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS. In the multi-gate structure, by changing the gate voltage, the work function of the metal gate was adjusted to effectively mitigate the electric field formed in the drain region by approximately four orders. As an adopting multi-gate structure, band to band tunneling is suppressed and gate induced drain leakage current is reduced. We verified that the dual-gate structure had less leakage current than the poly-Si BCAT using the TCAD simulation. The reduction of leakage according to the number of gates is inferred by confirming the reduction in GIDL of the three-gate structure compared with the dual-gate structure. Furthermore, the SPICE simulation confirmed that the proposed select word-line circuit transmits different optimized voltages to multiple gates when it is off than while transferring the same voltage when on. This structure can also be extended for application to other DRAM structures, such as the vertical structure and 3D-stacked DRAMs.

Efficient Partially-parallel NTT Processor for Lattice-based Post-quantum Cryptography

https://doi.org/10.5573/JSTS.2022.22.6.459

(Soyeon Choi) ; (Yerin Shin) ; (Kiho Lim) ; (Hoyoung Yoo)

This paper presents a partially-parallel number theoretic transform (NTT) processor design for polynomial multipliers, which is a key component of a lattice-based cryptography. Since the data flow of NTT is similar to that of FFT, studies have been conducted to apply the FFT structure to fit the NTT structure. However, the previous architectures suffer from high hardware complexity and low throughput. Thus, we propose a new partially-parallel design that models the data reordering process and derives a generalized data reordering circuit. The proposed partially parallel design solved the problem of the previous architectures. Moreover, it provides imp-roved performance through efficient data reordering. Synthesis results shows that the proposed 8-parallel 512-point NTT processor achieves 15% to 76% improvements in terms of hardware efficiency compared to the previous architectures. As a result, the proposed NTT processor is a good solution in a more diversified lattice-based crypto-processor with constrained usage conditions.

A 28 Gb/s Receiver Front-end Capable of Receiving Wide Range Current Signal in 65 nm CMOS

https://doi.org/10.5573/JSTS.2022.22.6.475

(Daehyun Koh) ; (Daniel Jeong) ; (Jeongho Hwang) ; (Deog-Kyoon Jeong)

This paper presents a receiver front-end fabricated in a 65 nm CMOS process to receive a wide range of high current input from the avalanche photodiode (APD). The transimpedance amplifier (TIA) consists of a resistive feedback inverter and three cascaded Cherry-Hooper amplifiers (CHAs) to obtain a high gain-bandwidth product. The TIA automatically subtracts input DC current. In addition, using inductors in the Cherry-Hooper amplifiers, the bandwidth of the TIA is improved from 14 GHz to 29.5 GHz. The receiver front-end chip has an active area of 0.22 mm2, and its energy efficiency is 1.3 pJ/bit. Input DC current range is measured up to 3 mA at 28 Gb/s.

Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems

https://doi.org/10.5573/JSTS.2022.22.6.482

(Yujin Kyung) ; (Gwang Sub Kim) ; (Donghyun Baek)

This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-?m CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are ?204.3, ?211.07, ?220.29, and ?213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.

A Ka-band Power Amplifier with On-chip Power Detector in 0.15 μm GaAs pHEMT Technology

https://doi.org/10.5573/JSTS.2022.22.6.493

(Sanghoon Sim) ; (Laurence Jeon)

A three stage 28 GHz power amplifier (PA) with on-chip power detector is presented. A 0.15 μm GaAs pHEMT process is used to implement the power amplifier. The chip size is 2.09 mm × 1.28 mm including the on-chip power detector and I/O pads. The PA die chip is attached on a commercial open cavity QFN package to evaluate the performances in surface mount use. The on-chip power detector is designed with directional coupler using diode rectifier to monitor available output power from the PA. The detector output voltage is very coherent to the output power in the operation frequency from 26.6 GHz to 29.2 GHz, where the deviation of the detector output voltage is lower than ± 3.7 % up to 27.4 dBm output power. The output P1dB is over than 26.9 dBm, saturated output power is over 27.4 dBm, and the PAEmax is 25~30 % across the operation frequency.