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A Simple Timing-skew Calibration using Flip-flops for Time-interleaved ADCs

(Ji-Hun Lim) ; (Sang-Gyu Park)

This paper presents a simple timing-skew calibration circuit for time-interleaved ADCs. At the core of the skew calibration scheme lies a pair of D flip-flops to detect the sign of the relative timing between a channel clock and the reference clocks. The D flip-flops form a latch structure to detect the sign of timing skew. The detected sign of the timing skew is accumulated by counters and used to control shunt-capacitor-inverter variable delay lines to adjust the timing of the channel clocks. Although this scheme cannot remove the skew from mismatches after the timing comparison point, it should be able to reduce the bulk of the timing skew. The performance of the calibration circuit implemented using a 28 nm CMOS technology was verified by post-layout simulations.

A Low-power DRAM Controller ASIC with a 36% Reduction in Average Active Power by Increasing On-die Termination Resistance

(Won-Cheol Lee) ; (Ho-Jun Kim) ; (Hong-June Park)

A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm2, 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations.

Low Power RF Interface of the Near-field Communications Tag IC for Sensors

(In-Young Lee) ; (Donggu Im)

In this paper, we propose the RF interface of NFC tag IC which is necessary for transmitting the results obtained using blood glucose sensor, water quality sensor, gas sensor and radioactive sensor to portable devices such as mobile phones. The proposed RF interface complies with the ISO14443 type-A standard using 100% ASK and solves the power and clock generation difficulties by using the internal VTH canceling rectifier that is based on the high efficiency voltage doubler and the switching phase locked loop. In the measurement results, the internal VTH canceling rectifier in the RF interface shows more than 80% power efficiency from 100% ASK signal, and successfully generates 1.8 V / 2.5 V supply from the input signal power higher than 6 dBm through low loss voltage regulator. Additionally, we can verify that the proposed switching phase locked loop is locked at 8 dBm or higher input signal power and successfully demodulates ASK input signal.

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

(Jae-Hyuk Lee) ; (Jun-Ho Boo) ; (Jun-Sang Park) ; (Tai-Ji An) ; (Hee-Wook Shin) ; (Young-Jae Cho) ; (Michael Choi) ; (Jin-Wook Burm) ; (Gil-Cho Ahn) ; (Seung-Hoon Lee)

This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm2. The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.

Review of Short-circuit Protection Circuits for SiC MOSFETs

(Seungjik Lee) ; (Ockgoo Lee) ; (Ilku Nam)

Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are commonly used in the power transistor industry owing to their superior conductivity, low switching loss, high-frequency operation, and desirable thermal characteristics. However, the short-circuit withstand time of SiC MOSFETs is shorter than that of Si devices, which is disadvantageous in fault states. Gate drivers for SiC MOSFETs require short-circuit protection and soft termination circuits to detect short circuits and protect the power devices and systems from a short-circuit state. Thus, short-circuit protection circuits for SiC MOSFETs are reviewed in this paper. Accordingly, short-circuit detection circuits classified according to gate-source voltage (VGS), drain-source voltage (VDS), and drain-source current (IDS) detection methods are discussed. Moreover, the merits and demerits of soft termination circuits are reviewed.

Design of an Approximate Adder based on Modified Full Adder and Nonzero Truncation for Machine Learning

(Hyoju Seo) ; (Hyelin Seok) ; (Jungwon Lee) ; (Youngsun Han) ; (Yongtae Kim)

This paper proposes a novel approximate adder based on a modified full adder that exploits AND-based bit-by-bit carry prediction and OR-based summation, and nonzero truncation scheme. The proposed adder design offers good tradeoff between the computation accuracy and hardware efficiency. When implemented in 32-nm CMOS technology, the proposed adder improves the area, power, and energy by up to 48.9%, 45.6%, and 45.4%, respectively, compared to existing approximate adders considered in this paper. Furthermore, our adder demonstrates excellent processing quality with remarkably reduced hardware resource when applied to image processing and machine learning applications.