Mobile QR Code QR CODE

Analytical Heat Transfer Model for a TTSVs-based Thermal Mitigation Power Chip

(Yongyong Wang) ; (Fashun Yang) ; (Kui Ma)

The work develops an analytical thermal model for a thermal Through Silicon Vias based heat mitigation power chip whose thermal path is quite different compared to the literatures published. Thermal spreading angle and transverse heat transfer of thermal Through Silicon Vias as well as its thermal stress impact on carrier mobility in active areas have been considered. Traditional one-dimensional thermal model used in three-dimensional integrated circuits and finite element analysis result are used to verify the accuracy of the proposed model. Temperature rise for the proposed structure with respect to the filling-via radius, bulk Si thickness, Through Silicon Via liner thickness and bonding layer thickness are investigated. It can be found that the proposed thermal model is superior than one-dimensional model in contrast with the simulation result which indicates an improvement in the thermal management of thermal Through Silicon Vias based three-dimensional integrated circuits associated with thermal-mechanical reliability.

Neural Spike Detection Circuit with Amplification Method using Input DC Level Control

(Jong Pal Kim)

A neural spike detection circuit is presented, in which all the amplifiers have an open loop architecture to reduce area and current consumption fundamentally. A new method for controlling the gain of an open loop amplifier is proposed. The gains of instrumentation amplifier (IA) and multiplier are controlled by a DC level of the input. In addition, an instrumentation amplifier (IA) includes a compensation circuit against the fabrication process corners to prevent amplification failure. The compensation circuit detects and adds threshold voltage variations in the compensation feedback loop. The circuit is fabricated using the standard 0.18 μm CMOS process. Changing the DC level at the IA input results in the amplification gain increase up to 650 V/V. The nonlinear amplification control capability of the multiplier is verified as the DC input level changes. The minimum detectable amplitude of neural spike is 100 μVpk. The overall power consumption is 1.4 μW. Integrated input-referred noise is measured to be 7.1 μVrms in a frequency range of 100 Hz to 10 kHz.

Effects of Oxygen Injection Rates on a-IGZO Thin-film Transistors with Oxygen Plasma Treatment

(Jae-Yun Lee) ; (Kwan-Jun Heo) ; (Seong-Gon Choi) ; (Heung Gyoon Ryu) ; (Jung-Hyuk Koh) ; (Sung-Jin Kim)

In this study, investigate the influence of oxygen plasma treatment on the oxide channel layer of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors based on the amount of oxygen gas injected. The a-IGZO channel layer thin-film transistors (TFTs) were fabricated with plasma treatment of zero, three, six, or nine standard cubic centimeters per minute (sccm) of oxygen gas injection into the a-IGZO channel layer using gun-type plasma cells from a molecular beam epitaxy system after the post-annealing process. In this experiment, oxygen plasma treatment on the a-IGZO channel layer improved the electrical and surface-area performance. Of all the treatment conditions, the a-IGZO channel layer TFT treated with plasma from an injection of 6 sccm of oxygen gas showed excellent transfer characteristics. They include saturation mobility of 14.4 cm2/Vs, a threshold voltage of 4.5 V, an on/off current ratio of 1.1 × 108, and an inverse subthreshold slope of 0.7 V/dec. Surface morphology analyses confirmed that increases in the oxygen gas injection rate decreased. A dynamic inverter test was conducted by configuring the logic circuit for the a-IGZO channel layer TFT, which verified the possibility for future application of the backplane device in active-driven displays.

High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

(Kyunghwan Min) ; (Sanggeun Lee) ; (Taehyoun Oh)

A phase interpolator (PI) based all-digital clock and data recovery (CDR) system has been fabricated in 65 nm CMOS process. The segmented switching units control the slew rate of input clock signal in the PI and the linearity of PI control code and output phase shift steps is improved by 0.4 LSB for standard deviation of differential nonlinearity (DNL). The measurement results show that our CDR locks successfully for 6 Gbit/s non-return to zero (NRZ) high-speed signal with 231-1 pseudo-random bit sequence (PRBS) pattern. The input NRZ input signal has 2.05 ps of root-mean square (RMS) jitter and 1 Vdpp of swing. When the loop is locked, the output clock signal shows 12.2 ps of peak-to-peak jitter and 1.826 ps of RMS jitter, which is divide 16 speed of the full rate. The measured phase noise of the recovered clock is -114.72 dBc/Hz at 1 MHz offset. The designed built-in pattern checker in receiver exhibits 10-12 of bit error rate (BER) at the center of data eye. The lock time of the loop measured via 7-bit monitoring digital-to-analog converter (DAC) is 54.5 ns. The prototype CDR occupies 0.073 mm2 chip area and consumes 17.4 mW from 1.0 V power supply.

Phonons and Valence-band Splitting in Strained GaAs1-xNx/GaAs Epilayers

(Tae Soo Jeong) ; (Hyeoncheol Kim) ; (Sukill Kang) ; (Kyu-Hwan Shim) ; (Taek Sung Kim)

The strain effects in strained GaAs1-xNx epilayers are characterized by Raman spectroscopy and photocurrent spectra at various nitrogen composition. In addition, the nitrogen composition and the strain were determined by using high-resolution X-ray diffraction (HR-XRD). The Raman spectra are observed to be dominated by the GaAs-like longitudinal optical (LO) phonon mode as the strongest peaks show up around 289~294 cm-1. Moreover, the weak and broad peaks features in the range of 255~276 cm-1 originate from the peaks of GaAs-like transverse optical (TO) phonon mode and disorder induced, GaN-like LO. And the Raman peak shifts toward lower wave number with increasing nitrogen compositions, which is indicates the presence of tensile strain in the strained GaAs1-xNx epilayers. The valence-band splitting of GaAs1-xNx are obtained from photocurrent spectra. As the nitrogen concentration increases, the tensile strain in strained GaAs1-xNx epilayers increases while the valence-band splitting increases.

Scalable Fabrication of Flexible Large-area Inverted Organic Photovoltaic Cells

(Jae Ha Myung) ; (Sung-Jin Kim) ; (Hyojin Kim) ; (Changhun Yun) ; (Moon Hee Kang)

Scalable large-area inverted organic photovoltaic (OPV) cells were fabricated on a flexible polyethylene naphthalate (PEN) substrate. To account for the scalability and impact of the substrate (rigid versus flexible), OPVs of various sizes (0.04?1.6 cm2) were fabricated on flexible PEN and rigid glass substrates. A single OPV cell area of up to 1.6 cm2 can be fabricated using a solution process at a low temperature of < 160 ℃. It should be noted that all processes except those of the electrodes were conducted based on a solution process under ambient air conditions, not inside a N2 filled glove box. It was found from the numerical calculations and experimental measurements that a lower photoconversion efficiency (PCE) for higher areas mainly comes from a degradation in the fill factor (FF). Solar cell characteristic parameters were measured under an AM1.5G spectrum (intensity of 100 mW/cm2), and the PCE was 1.8% and 2.0% for the OPV on the PEN and glass substrates, respectively.

Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing

(Dong-Woo Cha) ; (Jun-Young Park)

Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal conductivity and thermal isolation is suggested for better power management. Finally, time-dependent characteristics with various thicknesses of buried dielectric layer are discussed to improve annealing speed. As a result, the contents of this paper provide a guide to better application of ETA.

A 28-nm CMOS 11.2-Gbps Receiver based on Adaptive CTLE and Adaptive 3-Tap DFE With Hysteresis Low-pass Filter

(Myung-Hun Jung) ; (Yongsam Moon)

This paper proposes a receiver design incorporating both an adaptive continuous-time linear equalizer (CTLE) and an adaptive decision-feedback equalizer (DFE). The CTLE utilizes a merged rectifier and error amplifier, improving the DC gain and reducing the current consumption. Offset cancelation of the CTLE is performed by adaptively adjusting the load resistance of a CTLE cell. The DFE adopts the technique of using a slave latch behind a current summer for the relaxed timing constraint but excludes other auxiliary circuits that perform a master-latch function. The proposed low-pass filter with a hysteresis can suppress the oscillation of the DFE tap coefficients and the data level in the steady state. Fabricated in 28-nm CMOS process, the prototype receiver shows that the measured BER is less than 10?14 at 10.4 Gb/s for an 18-inch FR4 trace and at 11.2 Gb/s for a 12-inch FR4 trace, respectively, with both the adaptive CTLE and the adaptive DFE activated. Operating at 11.2 Gb/s, the energy efficiency of the receiver is 5.36 pJ/bit.