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Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique

https://doi.org/10.5573/JSTS.2021.21.5.297

(Ki-Hyun Kim) ; (Ji-Hyun Baek) ; (Jong-Hyun Kim) ; (Hyung-Il Chae)

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feed-forward (CIFF) architecture can achieve a high resolution and wide bandwidth with a high energy efficiency. Because it does not use the summation pre-amplifier, the energy efficiency obtained using the proposed ADC is higher than that of the TINS-SAR ADC based on the error-feedback (EF) architecture. In addition, the proposed ADC uses only one final residue sampling capacitor, and thus, the complexity of the circuit is reduced. The proposed ADC is implemented in a 65-nm CMOS process. According to the post-layout simulation result, a signal to noise and distortion ratio (SNDR) of 69.2 dB can be obtained for a sampling rate of 800 MS/s and bandwidth of 100 MHz with a high energy efficiency.

Inductorless Broadband Transimpedance Amplifier for 25-Gb/s NRZ and 50-Gb/s PAM-4 Operations in a 90-nm CMOS Technology

https://doi.org/10.5573/JSTS.2021.21.5.304

(Jau-Ji Jou) ; (Tien-Tsorng Shih) ; (Chih-Chen Peng) ; (Hao-Wen Hsu) ; (Xuan-Yi Ye)

In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 90-nm complementary metal-oxide-semiconductor (CMOS) technology. A regulated cascode circuit with low input impedance is used as the input stage of the TIA. The core amplifier is a fully differential amplifier with active feedback. The output stage of the TIA is an equalizer based on a differential amplifier with a source degenerated resistor and capacitor. The TIA has a bandwidth of 24.8 GHz and good linearity. In the TIA chip testing, clear 25-Gb/s nonreturn to zero and 50-Gb/s four-level pulse amplitude modulation eye diagrams can be observed.

Periodic Ground Structure for C-PHY Signaling in Mobile Applications

https://doi.org/10.5573/JSTS.2021.21.5.311

(TaeWoong Kim) ; (YoungBong Han) ; (Hung Khac Le) ; (JongWan Shim) ; (KwangMo Yang) ; (BumHee Bae) ; (SoYoung Kim)

In this paper, we propose periodic slit ground structure (PSG) to improve the signal integrity of multilevel signals at high data rate such as MIPI C-PHY. Periodic slits are added in the upper and lower ground planes of the stripline structure, without adding additional layers or increasing area, to reduce crosstalk among neighboring lines. The proposed PSG structure can effectively improve the eye-diagram, especially eye height (EH) in multilevel signaling. The effectiveness of the proposed structure is validated through simulation and measurement of PCB-flexible printed circuit board (FPCB)-PCB structure that emulates the interconnected system of MIPI C-PHY signal transmission in a mobile system. The measurements from the test structures show that at a 2.5 Gsps data rate condition, the PSG structures show improvement in EH and eye width (EW) by 38.6% and 9.7%, respectively, compared to stripline structures. The proposed idea can be generally applied in PCB designs that will be used in high speed multilevel signal transmission to improve EH.

An Electrical Stimulator IC with Chopped Pulse based Active Charge Balancing for Neural Interface Applications

https://doi.org/10.5573/JSTS.2021.21.5.322

(Jin-Young Son) ; (Hyouk-Kyu Cha)

In this paper, a current-mode neural stimulator integrated circuit (IC) using novel active charge balancing technique is presented. The charge balancing technique proposed in this work is based on chopped pulse waveform, where the number of chopped pulses generated in the anodic phase is controlled accurately in order to limit the amount of residual potential at the electrode. In addition, a quick automatic electrode shorting process follows the active charge balancing phase to further discharge to a negligible residual voltage level in every stimulation cycle, ensuring a safe and long-term operation. Both symmetric and asymmetric stimulation pulse waveforms can be selected to provide wide flexibility for various stimulation environment. The stimulator IC designed using 0.18-μm standard CMOS process achieves 12.3 V of voltage compliance and can deliver 1 mA of maximum stimulation current with 5-bit resolution and high linearity. All circuit functions are integrated on-chip without external components, and the fabricated chip consumes only 0.095 mm2 of active die area.

Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND

https://doi.org/10.5573/JSTS.2021.21.5.334

(Dae-Han Jung) ; (Khwang-Sun Lee) ; (Jun-Young Park)

Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing density. However, potential transfer through the silicon substrate or metal bit-line (BL) is insufficient with the increased number of stacks. Hence, we propose a novel V-NAND structure including multi-layered macaroni filler. The proposed macaroni filler is composed of a dielectric outer layer and a metallic core layer. The metallic core layer makes back-biasing is possible in V-NAND. As a result, erase speed can be improved without large modification of fabrication process or device layout.

CMOS Diodes under Cryogenic Temperature and High Magnetic Field Environment

https://doi.org/10.5573/JSTS.2021.21.5.340

(Dongha Shim)

This paper describes the DC characteristics of three CMOS diodes (PN junction diode, STI separated SBD (Schottky Barrier Diode) and Poly-gate separated SBD) under cryogenic temperature and high magnetic field environment. The temperature dependences of the devices were measured at the ambient temperatures of 300 K, 150 K, 77 K and 4.2 K. To understand the magnetic field dependence of the CMOS diodes at the temperatures, measurements were also performed under magnetic fields of 0 T, 2 T, 4 T and 6 T. The parameters including ideality factors, Schottky barrier heights, turn-on voltages and magnetoresistances (MR) of the diodes are analyzed under the various conditions. No abnormal behaviors are observed at the temperatures down to 4.2 K. The measured MRs vary depending on the diode current level. The maximum magnetoresistance of 35% is observed in the PN junction diode under the temperature of 4.2 K and horizontal magnetic field of 6 T. The MR quadratically increases as the magnetic field increases in the high injection region. The diodes show a higher magnetoresistance under a lower temperature and higher magnetic field. The results show the feasibility of CMOS diode circuits under the cryogenic temperature and high magnetic field environment.

Three-dimensional Modeling for the Transmittance of ITO/Mesh-Ag/ITO Multilayers using FDTD

https://doi.org/10.5573/JSTS.2021.21.5.348

(Eou-Sik Cho) ; (Sang Jik Kwon)

In order to improve the transmittance of ITO/Ag/ITO multilayers, Ag layer was formed with mesh structure. For more accurate and practical analysis, we performed the simulations using an optical wave simulator termed the full-wave simulation program. In our simulations, the three dimensional (3D) finite-difference time-domain (FDTD) method was used to realize the high density mesh structure, and a plane wave with variable wavelengths ranging from 250 to 850 nm is incident in the z-direction at normal incidence to the ITO/Mesh-Ag/ITO film surrounded by free-air space. From the simulation results, at a higher open ratio and lower Ag thickness, the transmittance of ITO/Mesh-Ag/ITO were not influenced by other parameters. Experimental measurements were performed depending on the various Ag mesh-spaces and mesh-widths. The open ratio of about 60 % has shown the acceptable results in the points of both the optical transmittance and the electrical conductance.

A Concurrent Dual-band CMOS Partial Feedback LNA with Noise and Input Impedance Matching Optimization for Advanced WLAN Applications

https://doi.org/10.5573/JSTS.2021.21.5.356

(Dong-Myeong Kim) ; (Euibong Yang) ; (Donggu Im)

A concurrent dual-band CMOS partial feedback LNA optimizing noise and input reflection coefficient (S11) at both 2.4 and 5.2 GHz frequency bands is designed using a 65-nm CMOS process for advanced WLAN applications. The inverter-based input transconductance stage directly drives two parallel cascode transistors with 2.4 and 5.2 GHz LC loads, and the output signals splitting into two resonators are combined through a complementary source follower (CSF). Based on an analytical study on the optimum noise impedance (Zopt) and minimum noise figure (NFmin) of the proposed concurrent LNA circuit topology, the concurrent dual-band input matching network is designed in order to achieve low noise figure (NF) around NFmin at both operating frequencies. By employing a partial resistive feedback between 2.4 GHz LC resonator and input transconductance stage through a CSF, an imperfect S11 of the proposed LNA at 2.4 GHz is improved at the expense of a slight increase of NF. In the simulation, the designed LNA achieved forward gain (S21) of 14 and 15.5 dB, NF of 1.6 and 2.2 dB, and S11 of -11.2 and -10.3 dB at 2.4 and 5.2 GHz, respectively. The power consumption of the designed LNA is 7.7 mW from a 1.2 V supply voltage.

2.4 GHz Low-power Receiver Front-end Employing I/Q Mixer with Current-reused Quadrature Transconductor for Bluetooth Low Energy Applications

https://doi.org/10.5573/JSTS.2021.21.5.364

(Sengjun Jo) ; (Hyeonjun Kim) ; (Kuduck Kwon)

In this paper, a 2.4 GHz Bluetooth low energy (BLE) receiver front-end with a new in-phase/quadrature (I/Q) down-conversion active mixer employing a current-reused quadrature trans-conductor is presented for low-power low-voltage Internet of Things applications. In the proposed I/Q mixer, the current-bleeding circuit, whose main role is to reduce the flicker noise in the switching stage, enhances the overall transconductance and provides quadrature signals with the main quadrature transconductor. Consequently, it improves the conversion gain and noise figure of the mixer without additional power consumption. The proposed BLE receiver front-end consists of a current-reused push-pull low-noise amplifier and an I/Q mixer with a current-reused quadrature transconductor. Simulated in a 65 nm CMOS process, the designed receiver front-end achieves a noise figure of 3.3 dB, conversion gain of 37.6 dB, and input-referred third-order intercept point of ?22.73 dBm. It draws a bias current of 1 mA from a nominal supply voltage of 1 V. The active die area is 0.5 mm2.