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Development of Organic Thin-film Transistors on a Biocompatible Parylene-C Substrate

(KyungMin Kim) ; (Sookyeong Kim) ; (Ah-Hyun Hong) ; (Yoojeong Ko) ; (Hyowon Jang) ; (Hyeok Kim) ; (Dong-Wook Park)

Organic thin-film transistors (OTFTs) fabricated on a biocompatible Parylene-C substrate can be applied to biosensors using a simple and cost-effective process. In this study, we developed biocompatible OTFTs by using organic materials to fabricate the substrate, gate dielectric, channel, and passivation layer. Poly(3-hexylthiophene) (P3HT) was used to fabricate the OTFTs on a Parylene-C-based platform. As the gate dielectric, Parylene-C showed promising insulation properties. Finally, we generated a cyclic olefin polymer (COP) passivation layer to protect P3HT from oxygen and moisture, and the effect of the COP passivation layer on the P3HT channel was analyzed. The proposed materials and fabrication methods will be useful for various bio-applications of OTFTs.

Electrical Performance Depending on the Grain Boundary-location in the Multiple Nanosheet Tunneling Field-effect Transistor based on the Poly-Si

(Ga Eon Kang) ; (Sang Ho Lee) ; (Jin Park) ; (So Ra Min) ; (Geon Uk Kim) ; (Jun Hyeok Heo) ; (Jaewon Jang) ; (Jin-Hyuk Bae) ; (Sin-Hyung Lee) ; (In Man Kang)

In this study, we present the electrical characteristics of the multiple nanosheet tunneling field-effect transistors (MNSTFETs) based on the polycrystalline silicon (poly-Si) depending on the grain boundary (GB)-locations. The effects of the GB are analyzed for 5 locations and they are compared with the device without the GB. When the GB was located in the tunneling region, the electrical performances were the most inferior compared with the device without the GB. In addition, it shows the electrical characteristics of 125 samples of the MNSTFETs compared with the multiple nanosheet metal-oxide-semiconductor field-effect transistors (MNSMOSFETs). The standard deviations (SDs) of the threshold voltage (VT) of MNSTFET and MNSMOSFET are 3.90 mV and 8.31 mV, respectively. If the GB is not located at 24 nm, the SDs of the average of subthreshold swing (SSave) are 1.50 mV/dec and 4.16 mV/dec, respectively. This simulation shows that the MNSTFET has smaller effect depending on the GB location than the MNSMOSFET.

Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates

(Jun Hyeok Heo) ; (Sang Ho Lee) ; (Jin Park) ; (So Ra Min) ; (Geon Uk Kim) ; (Ga Eon Kang) ; (Jaewon Jang) ; (Jin-Hyuk Bae) ; (Sin-Hyung Lee) ; (In Man Kang)

In this study, the multiple fin-type vertical GaN power transistor based on the GaN-on-GaN were analyzed using the two-dimensional technical computer-aided design (2-D TCAD) simulations. In the field of the electric vehicle systems requiring a high operation voltage of 1,000 V or more, the power devices have a large device area because of the long distance between the gate region and the drain region. This problem can be addressed by using the fin-type vertical GaN power transistor, which can reduce the device area due to its vertical channel. For the high current performance, the multiple fin-type structure was required. Thus, we investigated characteristics depending on the number of fin (Nfin). By comparing the on-state drain currents (Ion), the breakdown voltages (BV), and the on-resistances (Ron) with different Nfin, this study provides an understanding of the electrical properties of the multiple fin-type vertical GaN power transistor affected by Nfin.

Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA

(Guard Kanda) ; (Kwangki Ryoo)

Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge-Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.

A Spread Spectrum Clock Generator with Dual-tone Hershey-Kiss Modulation Profile

(Seongho Kim) ; (Taek-Joon An) ; (Yongwoo Kim) ; (Jin-Ku Kang)

This paper presents a spread spectrum clock generator (SSCG) using a dual-tone Hershey-Kiss modulation profile. The modulation controller has two up/down counters and one delta-sigma modulator, and the output of the modulation controller is provided to a multi-modulus divider in a fractional-N PLL. The proposed SSCG is designed to operate in either single-tone modulation mode or dual-tone modulation mode. Once the targeted modulation frequency and spread ratio are given, the design variables for the SSCG can be controlled digitally. The proposed SSCG was designed and fabricated using the 65 nm CMOS process and consumes 8.5 mW while generating a 5 GHz spectrum-spread clock signal with 1.2 V supply voltage. After all design parameters are set for a 0.5% spread ratio using 30 and 33 kHz modulation frequencies, the measured EMI reduction is 24.6 dB while single-tone modulation is applied and 28.7 dB while dual-tone modulation is applied.

Feasibility Study of Monitoring of Particle Generation in Plasma Etching Process by Plasma Impedance Measurement

(Yuji Kasashima) ; (Tatsuo Tabaru) ; (Takashi Ikeda)

In plasma etching process at LSI mass-production line, the particles cause the decrease in the production yield and the overall equipment effectiveness (OEE). In this study, the particles, which originate from etching reaction product, are investigated under the condition that a gas shower type electrode made from the developed MgO-based ceramics is used and a Si wafer is etched by using SF6 gas. We have demonstrated that plasma impedance monitoring method can monitor the tendency of particle generation caused by the flaking off of the film deposited on chamber inner walls. This non-invasive measurement method can be easily applied to the process equipment at mass-production line therefore the results can contribute to improvement of the production yield and the OEE.

A 0.9 - 1.5 GHz CMOS UWB Radar IC for Through the Wall Human Detection

(Byeong Jae Seo) ; (Gu Jung) ; (Sunghun Jung) ; (Dong-Min Seol) ; (Sungmoon Chung) ; (Yun Seong Eo)

In this paper, a UWB radar IC for the through wall radar is presented to achieve the smaller form factor of the module and low power operation. For the penetration performance enhancement, the radar IC s designed for the lower 0.9 ? 1.5 GHz band. The radar IC employs the 4-channel time-interleaved equivalent time sampling receiver for 200 ps fine resolution, and the digitally synthesized impulse generator for the transmitter. The human target behind the concrete brick wall can be detected in the distance over 9.4 m with the help of signal processing part and additional amplifiers. The radar transceiver IC is fabricated in a 0.13 μm CMOS technology and the current consumption is 116.3 mA at the 1.2 V supply.

1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement

(Si-Won Lee) ; (Seongjae Cho) ; (Il Hwan Cho) ; (Garam Kim)

In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read “1” retention time can be increased. The fabrication process is also proposed.

Effects of Oxygen Content on Output Characteristics of IGZO TFTs under High Current Driving Conditions

(Chae-Eun Oh) ; (Hwan-Seok Jeong) ; (Su-Hyeon Lee) ; (Dong-Ho Lee) ; (Yeong-Gil Kim) ; (Myeong-Ho Kim) ; (Kyoung Seok Son) ; (Jun Hyung Lim) ; (Sang-Hun Song) ; (Hyuck-In Kwon)

We study the effects of oxygen content in indium-gallium-zinc oxide (IGZO) thin films on the output characteristics of IGZO thin-film transistors (TFTs) under high current driving conditions. Output curves were characterized at a high gate-to-source voltage (= 40 V) from both oxygen-rich and oxygen-poor IGZO TFTs. Characterization results showed that the drain current (ID) decreased with an increase in the drain-to-source voltage (VDS) under high-VDS conditions in the oxygen-rich IGZO TFTs, but abruptly increased with VDS in the oxygen-poor IGZO TFTs. From the detailed analysis of the transfer and capacitance-voltage curves obtained after output curve characterization by varying the VDS sweep range, the abnormal behavior of the output curves was mainly attributed to the increased number of trapped electrons within the gate dielectric and that of the doubly ionized oxygen vacancies in IGZO during the output curve characterization at high VDSs in oxygen-rich and oxygen-poor IGZO TFTs, respectively. The abnormality of the output curve was more significant in a wider channel device in both TFTs, which was attributed to the increased device temperature due to the self-heating effects.

Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses

(Dong-Ho Lee) ; (Hwan-Seok Jeong) ; (Yeong-Gil Kim) ; (Myeong-Ho Kim) ; (Kyoung Seok Son) ; (Jun Hyung Lim) ; (Sang-Hun Song) ; (Hyuck-In Kwon)

In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔVTH) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiOX gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔVTH originated from each degradation mechanism using the subgap density of states-based ΔVTH decomposition technique for TFTs with different channel widths. Although every ΔVTH from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiOX gate dielectric was the dominant reason for the larger ΔVTH under SHS in IGZO TFTs with a wider channel width.