Mobile QR Code QR CODE

Deep Learning Segmentation Modeling for SiN, SiO2 Film Deposition Process Defect of High Bandwidth Memory

(Intae Whoang) ; (Chinkwan Cho) ; (Jin Hee Hong) ; (Dong Hee Son) ; (Byung Yoon Lim) ; (Jin Pyung Kim) ; (Kijun Bang)

At SK hynix Wafer Level Package (WLPKG) line, there are plenty of measuring and inspection steps to ensure the quality of High Bandwidth Memory (HBM). Although most of the measuring and inspection steps are handled automatically, some of the steps still need confirmation from line operators with their naked eye and skills. Since the operators' skills are different, sometimes it causes human errors, and these risks become chronic problems for the company. To solve this problem, Package & Test (P&T) group at SK hynix has been steadily promoting the inspection automation system using deep learning. However, deep learning has the disadvantage of not providing interpretation information, such as which area is actually defective in the target image and its shape for the ‘Excellent’ result of outputs. In this paper, we will introduce cases in which defect patterns are automatically extracted from inspection images taken during the SiN / SiO2 film deposition process by using two deep-learning segmentation models. The performance of the technology to be introduced was demonstrated by comparing the Mean IoU value between the extracted defect image and label mask. Through the proposed technology, we intend to contribute to unmanned inspection verification tasks in the future and accelerate the realization of Industry 4.0.

Resistive Hydrogen Detection Sensors based on 2 Dimensions ? Molybdenum Disulfide Decorated by Palladium Nanoparticles

(DongJun Jang) ; (U Jin Cho) ; (Youhyeong Jeon) ; (TaeYong Lee) ; (RyangHa Kim) ; (Younglae Kim) ; (Min-Woo Kwon)

This research presents a resistive-type hydrogen (H2) gas sensor based on a composite of palladium nanoparticles (Pd-NP) decorated on 2D-molybdenum disulfide (MoS2) layer. The sensor fabrication involves synthesizing MoS2 and coating Pd by DC sputtering technique. MoS2 has been adopted for its high selectivity for H2, wide operating temperature range, reliability, and low power consumption. Pd has high catalytic properties for H2 and performs a H2 adsorption mechanism through resistance transition. In this study, we propose a Pd-decorated MoS2 structure and introduce the chemical resistance mechanism within the channel. The limit of detection (LOD), sensitivity and response time of the fabricated H2 gas sensors are optimized and analyzed. Finally, the nanocomposites network based H2 sensor can promote the utilization of various industries and discuss the issues in sensor applications.

A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2nd Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control

(Byeong-Ho Yu) ; (Jun-Ho Boo) ; (Jae-Geun Lim) ; (Hyoung-Jung Kim) ; (Jae-Hyuk Lee) ; (Gil-Cho Ahn)

This paper presents a 2nd order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.

Empirical Analysis of Disaggregated Cloud Memory on Memory Intensive Applications

(Yeonwoo Jeong) ; (Gyeonghwan Jung) ; (Kyuli Park) ; (Youngjae Kim) ; (Sungyong Park)

Disaggregated Cloud Memory (DCM) is a hypervisor-based solution that allows client node to extend local memory by leveraging underutilized memory from remote node. These two nodes are generally connected through Remote Direct Memory Access (RDMA)-based high-bandwidth InfiniBand networks. DCM has been a viable alternative to mitigate the performance degradation of memory-intensive applications in memory-constrained environments. There has also been a growing interest in developing memory-intensive applications with managed languages (we call managed applications) such as Java and Python. These managed languages are easy to use but introduce unpredictability in memory usage at runtime. Despite the advantage of memory extension in DCM, the empirical studies that analyze the performance impact and overhead of running managed applications in DCM are lacking. This paper presents the results of a comprehensive study of DCM on both managed and unmanaged applications. The experimental results revealed that the performance degradation of unmanaged applications in DCM is only less than 6% due to fast remote paging and optimized page eviction policy. However, Garbage Collection (GC) severely degrades the performance of managed applications when page fault occurs, while DCM mitigates the performance degradation efficiently.

Security Problems of Latest FPGAs and Reverse Engineering Methods of Xilinx 7-series FPGAs

(Dongchan Lee) ; (Sanghyun Lee) ; (Mannhee Cho) ; (Hyung-Min Lee) ; (Youngmin Kim)

Field programmable gate arrays (FPGA) are commonly used in modern electronic applications, such as home appliances, automobiles, aerospace applications, and Internet of Things (IoT). However, security research is still insufficient compared to the rapidly developing design using FPGA. Attackers frequently attempt to hack into the vulnerable security of FPGA and introduce malicious codes, such as trojan. To defend against these attacks, it is necessary to determine the structure of FPGA accurately and study hackers' attacks. In this paper, we first explain the basic structure of FPGA, bitstream generation process, bitstream format, and structural differences between the Xilinx Vivado and ISE tools. We also reveal the vulnerabilities of the encryption method of IEEE 1735, which is widely used as a security method, and introduce security vulnerabilities to representative FPGA suppliers using IEEE 1735. Moreover, we analyze the security issues that can occur during the bitstream generation process and explain the recent research trend of reverse engineering against these security vulnerabilities.

Charge Trap Flash structure with Feedback Field Effect Transistor for Processing in Memory

(Junhyeong Lee) ; (Misun Cha) ; (Min-Woo Kwon)

Recently, a memory wall has become a concern due to the increasing distance between memory and CPU in the von Neumann structure. While the CPU and logic devices operate quickly, their speed becomes irrelevant due to the slow data transfer between them. Consequently, addressing the data delay problem between the CPU and the logic elements is crucial. To tackle this issue, researchers have been exploring the Processing in Memory (PIM) technology, which enables simultaneous memory and computation. However, traditional volatile or nonvolatile memory-based PIM approaches have inherent limitations in overcoming the memory wall problem, as memory and computation are performed sequentially on separate devices. Therefore, there is a need to develop a new memory-logic device capable of performing read and operation simultaneously. In this paper, we propose a Feedback Field Effect Transistor (FBFET) with a charge trap layer that can fulfill both memory and computational roles, thus implementing an ideal Processing in Memory technology. The device features an oxide-nitride-oxide structure, where nitride is coupled to the oxide side of the FBFET. It accumulates electric charges in the floating body for memory operations and reads the data stored in the charge trap layer for logic operations. By selecting the control gate bias, the computing operation can be configured to perform AND or OR operations. This enables simultaneous memory and logical operations to take place.

A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder

(Jeong-Mi Park) ; (Jin-Ku Kang)

This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System's Spectre. A channel with 15.36 dB loss at Nyquist frequency was compensated through a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA). The simulation results demonstrate proper convergence of threshold voltage and reduce the threshold adaptation time compared to the conventional. The power consumption of the receiver is only 29 mW. The power efficiency of the receiver is 1.45 pJ/bit.

A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors

(Dong-Hwan Seo) ; (Jung-Gyun Kim) ; (Byung-Geun Lee)

This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metal-oxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.

In-depth Survey of Processing-in-memory Architectures for Deep Neural Networks

(Ji-Hoon Jang) ; (Jin Shin) ; (Jun-Tae Park) ; (In-Seong Hwang) ; (Hyun Kim)

Processing-in-Memory (PIM) is an emerging computing architecture that has gained significant attention in recent times. It aims to maximize data movement efficiency by moving away from the traditional von Neumann architecture. PIM is particularly well-suited for handling deep neural networks (DNNs) that require significant data movement between the processing unit and the memory device. As a result, there has been substantial research in this area. To optimally handle DNNs with diverse structures and inductive biases, such as convolutional neural networks, graph convolutional networks, recurrent neural networks, and transformers, within a PIM architecture, careful consideration should be given to how data mapping and data flow are processed in PIM. This paper aims to provide insight into these aspects by analyzing the characteristics of various DNNs and providing detailed explanations of how they have been implemented with PIM architectures using commercially available memory technologies like DRAM and next-generation memory technologies like ReRAM.