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Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

(Ho-Jun Kim) ; (Won-Cheol Lee) ; (Hong-June Park)

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation.

Investigation of Mechanical Stability during Electrothermal Annealing in a 3D NAND Flash Memory String

(Yu-Jin Kim) ; (Jun-Young Park)

Simulation studies are performed for better mechanical stability during using electro-thermal annealing (ETA) in 3D NAND flash memory. It is revealed that the mechanical stress is closely associated with the cell temperature and thermal expansion characteristic. Based on the thermal and material knowledges, various approaches for reducing the mechanical stress are proposed in terms of modification of bias configuration, alternative materials, and novel structure.

A Study on SRAM Designs to Exploit the TEI-aware Ultra-low Power Techniques

(Seung-Yeong Lee) ; (Jae-Hyoung Lee) ; (Woojoo Lee) ; (Younghyun Kim)

Recently, temperature effect inversion aware ultra low power (TEI-ULP) techniques have been actively proposed to realize lower power above the existing ULP system-on-chips (SoCs) by utilizing the TEI phenomenon. Although these TEI-ULP techniques have been proven to have a significant power saving effect by applying them to logic parts in the actually fabricated SoC, SRAM has unfortunately been excluded from the benefits. This is because there has been no research on whether the TEI phenomenon occurs in ultra low voltage operating SRAM (ULV-SRAM) and, if so, whether the effect appears when TEI-ULP techniques are applied. In this paper, it is revealed for the first time that the TEI phenomenon occurs in the existing ULV-SRAM. In addition, this paper considers the stability problem of SRAM, which makes it difficult to apply the existing TEI-ULP techniques to ULV-SRAM, and proposes TEI-VSUS, a state-of-the-art TEI-ULP techniques to address this problem. Subsequently, this paper verifies the proposed TEI-VSUS in ULV-SRAM through intensive simulations, and the power saving rate for three representative ULV-SRAM models with different operations are acquired. Furthermore, an method to increase the power saving effect of TEIVSUS is proposed by relaxing the restrictions on stability so that the proposed technique can be used in a wider environment. The efficacy of the proposed method is also validated through simulations based on the ULV-SRAM models with the 28 nm FD-SOI process technology.

Sub-6 GHz Noise-cancelling Balun-LNTA with Dualband Q-enhanced LC Notch Filter for 5G New Radio Cellular Applications

(Donggu Lee) ; (Kuduck Kwon)

This paper presents a blocker-tolerant broadband balun-low-noise transconductance amplifier (LNTA) with a high-Q dual-band LC notch filter for 5G new radio (NR) sub-6GHz cellular applications. The proposed balun-LNTA employs a noise-cancelling 1:5 CG-CS balun-LNA topology with local feedback gm-boosting and modified currentbleeding techniques to support entire bands of sub-6 GHz 5G NR application with less than 5 dB NF performance and balanced output of balun-LNTA. The dual-band Q-boosted LC notch filter with a bandswitchable differential inductor is also proposed to enhance blocker tolerance of the receiver by removing out-of-band blockers and strong transmitter leakage signals. Simulated in a 65-nm CMOS process, the designed balun-LNTA achieves a minimum noise figure of 2.38 dB, a maximum transconductance gain of 44 mS, an S11 of less than ?10 dB over the frequency range of 50 MHz-6 GHz, an input-referred third-order intercept point of 1.82 dBm, and blocker rejection ratios of more than 15 dB. It consumes 5.9 mA from a nominal supply voltage of 1 V. Its active die area is 0.55 mm2.

High Resolution CMOS Frequency-to-digital Converter for a Fine Dust Sensor using a MEMS Resonator

(Hyunwon Moon)

A high resolution, low power CMOS oscillator and frequency-to-digital converter for a fine dust sensor using a MEMS resonator is proposed. The proposed frequency-to-digital converter is realized based on dual-loop hybrid delay-locked loop to distinguish fine frequency variations according to very small fine dust concentrations, and simultaneously applied binary and square search algorithms to obtain accurate digital codes indicating frequency changes. An oscillator and frequency-todigital converter for a fine dust sensor is implemented using the 0.18-μm CMOS process. The core size of the fabricated MEMS oscillator and frequency-to-digital converter is 0.9 mm2 and consumes about 16 mW of power at 1.8 V supply voltage. The proposed frequency-to-digital converter covers the input frequency range of 1.7 GHz to 2.3 GHz with 1 bit resolution of about 3 MHz.

A Quadrature Error Corrector for Aperiodic, Quarterrate Data Strobe Signals in HBM3 Interfaces

(Seo-Yeong Jo) ; (Jinhyung Lee) ; (Myeong-Jae Park) ; (Deog-Kyoon Jeong) ; (Jaeha Kim)

This paper proposes a quadrature error corrector (QEC) for the aperiodic, quarter-rate data strobe (DQS) signals in the high bandwidth memory generation 3 (HBM3) interfaces. Unlike the existing approaches, which are applicable to periodic clock signals only, the proposed QEC can adjust the phase spacings among four aperiodic, quarter-rate DQS signals to be equal to 1/4 of the operating clock period. Its pulse-width detector measures each phase spacing by charging a capacitor with a fixed current during the difference period and comparing its voltage against the voltage of a four-times larger capacitor charged for the whole clock period. The post-layout simulation results of a prototype QEC designed in a 40-nm CMOS process show that the QEC can correct the phase errors ranging -43.2~43.2° with errors less than 5.01° for both seamless and burst modes. The QEC consumes the maximum power of 2.42mW when operating at 1.6-GHz and 1.1-V supply, and occupies the active area of 0.01 mm2.

Nanoelectromechanical (NEM) Devices for Logic and Memory Applications

(Hyug Su Kwon) ; (Woo Young Choi)

Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

A Compact 6-bit Phase Shifter in 65 nm RF CMOS Technology for ISM Band

(Tan-Binh Ngo) ; (Quang-Huy Do) ; (Sang-Woong Yoon)

We presented a 6-bit switched-network type phase shifter, which was implemented in Samsung 65nm RF CMOS technology. The phase shifter was designed with lumped-element filter topologies using inductors and capacitors for compact size. For 64 states, in the frequency of 2.12 GHz - 2.51 GHz, measured insertion loss was -9.7±1.5 dB. The input and output return loss were above 8.2 dB and 10 dB, respectively. The rms phase error and rms amplitude error were less than 3° and 0.87 dB, respectively. The chip size with including pads was 1.4 × 0.81 mm2.