| Title |
Design of a Floating-bulk NMOS Triggered GGNMOS with Low Triggering Voltage and High Robustness Aimed at 3.3 V I/O ESD Protection |
| Authors |
(Haotian Chen) ; (Yang Wang) ; (Hongjiao Yang) ; (Liqiang Ding) ; (Wei Liu) ; (Jun Deng) ; (Fengfeng Zhou) ; (Beibei Nie) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.3.218 |
| Keywords |
Gate-grounded MOSFET (GGNMOS); Floating-bulk; holding voltage |
| Abstract |
GGNMOS is widely utilized as ESD protection device due to its simple structure and excellent process compatibility. The traditional multi-finger GGNMOS faces the problem of uneven current conduction. Moreover, under the application scenario of 3.3 V, the trigger voltage of GGNMOS is excessively high. This paper proposes a floating-bulk NMOS triggered GGNMOS (FBTGGNMOS), unlike previous studies, based on the standard 0.18um CMOS process, the FBTGGNMOS can achieve a relatively low trigger voltage without the need for additional detection circuits and control signals. FBTGGNMOS utilizes floating-bulk NMOS as its triggering structure, the factors contributing to the low BV of floating-bulk NMOS is investigated. TCAD simulation demonstrates the working mechanism of the device, the simulation results show that when ESD events occur, the added floating-bulk NMOS conducts first to provide triggering current for GGNMOS and help the device to conduct evenly. TLP test results demonstrate that, compared with traditional GGNMOS, FBTGGNMOS has a reduced trigger voltage by 41%, at only 5.24 V. With its low trigger voltage, high holding voltage, and high robustness, FBTGGNMOS can meet the requirements for 3.3 V I/O protection applications. |