| Title |
Design of IEEE 1500-compatible Test access mechanism for Tile-based AI semiconductor with Layout Mirroring |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.3.257 |
| Keywords |
Test access mechanism; IEEE 1500; AI semiconductor; Tile-based design; mirrored core layout |
| Abstract |
The IEEE 1500 standard provides robust test access for embedded cores but faces challenges in supporting tile-based designs with mirrored layout, which are commonly used in AI semiconductors. This paper introduces a novel design methodology for an IEEE 1500-compatible test access mechanism specifically developed to meet the requirements of AI semiconductor architectures. The proposed methodology leverages pass-through paths with bi-directional signaling, facilitating efficient reuse of tile layouts and enabling seamless integration of tile elements into chip designs. This approach significantly reduces development effort while maintaining design flexibility. Simulation results validate the effectiveness of the proposed test access mechanism, and two formulas are presented to optimize capture, update, and shift operating frequencies. Additionally, a pipelined path-through path design is proposed to improve the speed of IEEE 1500 shift operation. |