※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.
Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique
Inductorless Broadband Transimpedance Amplifier for 25-Gb/s NRZ and 50-Gb/s PAM-4 Operations in a 90-nm CMOS Technology
Periodic Ground Structure for C-PHY Signaling in Mobile Applications
An Electrical Stimulator IC with Chopped Pulse based Active Charge Balancing for Neural Interface Applications
Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND
CMOS Diodes under Cryogenic Temperature and High Magnetic Field Environment
Three-dimensional Modeling for the Transmittance of ITO/Mesh-Ag/ITO Multilayers using FDTD
A Concurrent Dual-band CMOS Partial Feedback LNA with Noise and Input Impedance Matching Optimization for Advanced WLAN Applications
2.4 GHz Low-power Receiver Front-end Employing I/Q Mixer with Current-reused Quadrature Transconductor for Bluetooth Low Energy Applications