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Probabilistic based CMOS Adder for High Speed Communication Systems
Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping
Silicon-controlled Rectifier-based Electrostatic Discharge Protection Circuit with Additional NPN Parasitic Bipolar Junction Transistor for 5-V Application
Handy Calibration Substrate for both Horizontal and Vertical Probing
6.5 kV SiC Power Devices with Improved Blocking Characteristics against Process Deviations
Body-biasing-based Latch Offset Cancellation Sensing Circuit for Deep Submicrometer STT-MRAM
An Approximate DRAM Design with an Adjustable Refresh Scheme for Low-power Deep Neural Networks
A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration
12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process
Effects of Ultrasonication on the Electrical Performance of a-IGZO TFTs