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2021-04

P.85

Probabilistic based CMOS Adder for High Speed Communication Systems

(S. Venkatesh Babu) ; (S. Arumugam)
https://doi.org/10.5573/JSTS.2021.21.2.085
P.92

Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping

(Young Suh Song) ; (Taejin Jang) ; (Hyun-Min Kim) ; (Jong-Ho Lee) ; (Byung-Gook Park)
https://doi.org/10.5573/JSTS.2021.21.2.092
P.109

Handy Calibration Substrate for both Horizontal and Vertical Probing

(Bo Pu) ; (Taeho Kim) ; (Jinho Joo) ; (Wansoo Nah)
https://doi.org/10.5573/JSTS.2021.21.2.109
P.119

6.5 kV SiC Power Devices with Improved Blocking Characteristics against Process Deviations

(Junki Jung) ; (Ogyun Seok) ; (In Ho Kang) ; (Hyoung Woo Kim) ; (Wook Bahng) ; (Ho-Jun Lee)
https://doi.org/10.5573/JSTS.2021.21.2.119
P.134

An Approximate DRAM Design with an Adjustable Refresh Scheme for Low-power Deep Neural Networks

(Duy Thanh Nguyen) ; (Hyun Kim) ; (Hyuk-Jae Lee)
https://doi.org/10.5573/JSTS.2021.21.2.134
P.143

A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration

(Hwan-Seok Ku) ; (Seungnam Choi) ; (Jae-Yoon Sim)
https://doi.org/10.5573/JSTS.2021.21.2.143
P.152

12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process

(Sanggeun Lee) ; (Taehyoun Oh)
https://doi.org/10.5573/JSTS.2021.21.2.152
P.157

Effects of Ultrasonication on the Electrical Performance of a-IGZO TFTs

(Jae-Yun Lee) ; (Kwan-Jun Heo) ; (Seong-Gon Choi) ; (Jung-Hyuk Koh) ; (Sung-Jin Kim)
https://doi.org/10.5573/JSTS.2021.21.2.157