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Title Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping
Authors (Young Suh Song) ; (Taejin Jang) ; (Hyun-Min Kim) ; (Jong-Ho Lee) ; (Byung-Gook Park)
Page pp.92-100
ISSN 1598-1657
Keywords SONOS memory; tunnel FET (TFET); erase speed; erase efficiency; nonvolatile charge trapping memory (CTM)
Abstract In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.