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Liu Y., Jan 2017, Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory, IEEE Electron Device Letters, Vol. 38, No. 1, pp. 48-51DOI
Hsieh E. R., Wang H. T., Chung S. S., Chang W., Wang S. D., Chen C. H., July 2016, Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory, 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 38-42DOI
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Kim T., Song Y. S., Park B. -G., Oct 2019, Overflow handling integrate-and-fire silicon-on-insulator neuron circuit incorporating a Schmitt trigger implemented by back-gate effect, Vol. 19, No. 10, pp. 6183-6186DOI
Lue H. -T., Dec 2005, BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability, IEEE International Electron Devices Meeting, pp. 547-550DOI
Song Y. S., et al. , June 2020, Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TAHOAOS (TaN/Al2O3/HfO2/ SiO2/Al2O3/SiO2/Si) structure, Japanese Journal of Applied Physics, Vol. 59, No. 6, pp. 061006-1Google Search
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Choi Y., Feb 2020, Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET, Solid-State Electronics, Vol. 164, pp. 107686-1-107686-7DOI
Wu K. -H., Chien H. -C., Chan C. -C., Chen T. -S., Kao C. -H., May 2005, SONOS device with tapered bandgap nitride layer, IEEE Transactions on Electron Devices, Vol. 52, No. 5, pp. 987-992DOI
Guan W., Long S., Liu M., Liu Q., Li Z., Jia R., May 2007, Modeling of retention characteristics for metal and semiconductor nanocrystal memories, Solid-State Electronics, Vol. 51, No. 5, pp. 806-811DOI
Liu Y., Tang S., Banerjee S. K., Jan 2006, Tunnel oxide thickness dependence of activation energy for retention time in SiGe quantum dot flash memory, Applied Physics Letters, Vol. 88, pp. 213504-1-213504-3DOI
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Wang S., April 2007, Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory, IEEE International Reliability Physics Symposium Proceedings, pp. 171-176DOI
Song Y. S., Kim J. H., Kim G., Kim H. -M., Kim S., Park B. -G., Improvement in Self-heating Characteristic by Incorporating Hetero-gate-dielectric in Gate-All-Around MOSFETs, IEEE Journal of the Electron Devices SocietyDOI
Song Y. S., May 2021, Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application, Journal of Nanoscience and Nanotechnology, Vol. 21, No. 5, pp. 3092-3098DOI
Lo R., May 2015, A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance, IEEE International Memory Workshop (IMW), pp. 1-4DOI
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Park Y., Dec 2006, Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology, International Electron Devices Meeting, pp. 1-4DOI
Padilla A., Liu T. K., Apr 2007, Dual-bit SONOS FinFET Non-Volatile Memory Cell and New Method of Charge Detection, 2007 International Symposium on VLSI Technology, Vol. systems and applications (vlsi-tsa), pp. 1-2DOI
Xuan P., She M., Harteneck B., Liddle A., Bokor J., King T. -., Dec 2003, FinFET SONOS flash memory for embedded applications, IEEE International Electron Devices Meeting 2003, pp. 26.4.1-26.4.4DOI
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Ko M. -D., July 2013, Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis, IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2721-2727DOI
Goswami R., Mar 2014, Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp+ Si1-xGex layer at source-channel tunnel junction, 2014 International Conference on Green Computing Communication and Electrical EngineeringDOI
Kim J. H., Aug 2020, Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor, Micromachines, Vol. 11, No. 8, pp. 780-789DOI