Mobile QR Code QR CODE


Verma N., Chandrakasan A. P., Jun 2007, An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes, IEEE J Solid-State Circuits, Vol. 42, No. 6, pp. 1196-1205DOI
Sharma A., Polley A., Lee S. B., Narayanan S., Li W., Sculley T., Ramaswamy S., Apr 2017, A Sub-60-μA multimodal smart biosensing SoC with > 80-dB SNR, 35-μA photoplethysmography signal chain, IEEE J Solid-State Circuits, Vol. 52, No. 4, pp. 1021-1033DOI
Harpe P. J. A., Gao H., Dommele R. V., Cantatore E., van Roermund A.H. M., Jan 2016, A 0.20mm2 3nW signal acquisition IC for miniature sensor nodes in 65 nm CMOS, IEEE J Solid-State Circuits, Vol. 51, No. 1, pp. 240-248Google Search
Zhu Z., Liang Y., Sep 2015, A 0.6-V 38-nW 9.4-ENOB 20-KS/s SAR ADC in 0.18-μm CMOS for medical implant devices, IEEE Trans Circuits Syst I Reg. Papers, Vol. 62, No. 9, pp. 2167-2176DOI
Mao W., Li Y., Heng C.-H., Lian Y., Feb 2019, A low-power 12-bit 1-kS/s SAR ADC for biomedical signal processing, IEEE Trans Circuits Syst I Reg Papers, Vol. 66, No. 2, pp. 477-487DOI
Lee C. C., Flynn M. P., Apr 2011, A SAR-assisted two-stage pipeline ADC, IEEE J Solid-State Circuits, Vol. 46, No. 4, pp. 859-869DOI
Xu H., Cai Y., Du L., Zhou Y., Xu B., Gong D., Ye J., Chiu Y., Feb 2017, A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS, in Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers San Francisco CA USA, pp. 476-477DOI
Maddox M., Chen B., Coln M., Kapusta R., Shen J., Fernando L., Nov 2016, A 16 bit linear passive-charge-sharing SAR ADC in 55 nm CMOS, in Proc IEEE Asian Solid-State Circuits Conf (A-SSCC), pp. 153-156DOI
Shim M., Jun 2016, An oscillator collapse-based comparator with application in a 74.1 dB SNDR, 20 KS/s 15 b SAR ADC, in Symp VLSI Circuits Dig Tech Papers Honolulu HI USA, pp. 1-2DOI
Harpe P., Cantatore E., van Roermund A., Feb 2014, An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR, in IEEE Int Solid-State Circuits Conf (ISSCC) Dig. Tech. Papers, pp. 194-195DOI
Hurrel C. P., Lyden C., Laing D., Dec 2010, An 18 b 12.5MS/s ADC with 93dB SNR, IEEE J. Solid-State Circuits}, Vol. 45, No. 12, pp. 2647-2654Google Search
Bannon A., Hurrell C. P., Hummerston D., Lyden and C., Jun 2014, An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in Symp VLSI Circuits Dig Tech Papers Honolulu HI USA, pp. 42-43DOI
Choi S., Ku H.-S., Son H., Kim B., Park H.-J., Sim J.-Y., Feb 2018, An 84.6-dB-SNDR and 98.2-dB-SFDR residue-integrated SAR ADC for low-power sensor applications, IEEE J Solid-State Circuits, Vol. 53, No. 2, pp. 404-417DOI
Hsu C.-W., Chang S.-J., Huang C.-P., Chang L.-J., Shyu Y.-T., Hou C.-H., Tseng H.-A., Kung C.-Y., Hu and H.-J., Mar 2018, A 12-b 40-MS/s calibration-free SAR ADC, IEEE Trans. Circuits Syst. I Reg. Papers, Vol. 65, No. 3, pp. 881-890DOI
Lee C. C., Lu C.-Y., Narayanaswamy R., Rizk and J. B., Jun 2015, A 12b 70 MS/s SAR ADC with digital startup calibration in 14 nm CMOS, in Proc. IEEE Symp. VLSI Circuits, Vol. kyoto, No. japan, pp. c62-C63DOI
McNeil J., Coln M. C. W., Larivee B. J., Dec 2005, ‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC, IEEE J. Solid-Sate Circuits, Vol. 40, No. 12, pp. 2437-2445DOI
Shen J., Shikata A., Fernando L., Guthrie N., Chen B., Maddox M., Mascarenhas N., Kapusta R., Coln and M., Jun 2017, A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, Vol. kyoto, No. japan, pp. 282-283DOI
Ding M., Harpe P., Liu Y.-H., Busze B., Groot H., Feb 2017, A 46μW 13 b 6.4 MS/s SAR ADC with background mismatch and offset calibration, IEEE J. Solid-State Circuits, Vol. 52, No. 2, pp. 423-432Google Search
Li H., Maddox M., Coin M. C. W., Buckley W., Hummerston D., Naeem N., Feb 2018, A signal-independent background-calibrating 20b 1MS/s SAR ADC with 0.3ppm INL, in Proc IEEE Int Solid-State Circuits Conf (ISSCC)}, Vol. san francisco ca usa, pp. 242-244DOI
Zhou Y., Xu B., Chiu Y., Apr 2015, A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector, IEEE J. Solid-State Circuits, Vol. 50, No. 4, pp. 920-931DOI
Zhang P., Feng W., Zhao P., Chen X., Zhang Z., 2019, A 16-bit 1-MS/s pseudo-differential SAR ADC with digital calbiration and DNL enhancement achieving 92 dB SNDR, IEEE Access, Vol. 7DOI
Liu J., Tang X., Zhao W., Shen L., Sun N., Dec 2020, A 13-bit 0.005-mm2 40-MS/s SAR ADC with kT/C noise cancellation, IEEE J. Solid-State Circuits, Vol. 55, No. 12, pp. 3260-3270DOI