KuHwanSeok^{1}
ChoiSeungnam^{1}
SimJaeYoon^{1}

(Electrical Engineering, Pohang University of Science and Technology, 77, Cheongamro,
Namgu, Pohangsi, Gyeongsangbukdo, Pohang 37673, Korea )
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Analogtodigital conversion (ADC), successive approximation register (SAR), calibration, highresolution ADC
I. INTRODUCTION
Successive approximation register (SAR) ADC has been the most preferred candidate
in lowpower sensor applications ^{(1}^{5)}. Though it can provide a burstmode conversion for the dutycycled system with superior
energy efficiency, achievable effective number of bits (ENOBs) are limited to 10~11b.
For sensor applications requiring an ENOB of over 14b, oversampling ADCs using deltasigma
modulators (DSMs) ^{(7}^{10)} have been general candidates, but at the cost of more energy consumption. To mitigate
the problem of comparator noise in SAR ADC, twostep pipelinedSAR architecture with
a gain stage between two SAR steps has been actively investigated ^{(6)}. However, the mismatch among capacitors and tightened requirement of highprecision
analog circuits for interstage processing eventually limit the maximum achievable
ENOBs.
Residueintegration (RI) SAR ADCs ^{(11}^{13)} have been also considered for fineprecision applications. Though they demonstrated
effectiveness both in robustness against comparator noise and in energy efficiency,
they require a highgain amplifier for RI ^{(11,}^{12)}. In ^{(13)}, combining a DSM in RI operation helps to relieve the constraint on the amplifier
gain. Though it reduces the requirement of highprecision analog circuits, mismatch
among capacitors is still left to be the performancelimiting factor. Adopting dynamic
element matching (DEM) can reduce the effect of capacitor mismatch. However, applying
DEM brings about complicated circuit blocks and is limited to only a part of capacitor
bank of SAR ADC ^{(13,}^{14)}.
The calibration technique has been considered to compensate for capacitor mismatches,
hence improving the code linearity ^{(15}^{20)}. The effect of capacitor mismatch could be also reduced by employing a redundancy
^{(15)}, but at the cost of complicated processing of sub2 radixbased conversion. As an
alternative approach, background calibration schemes ^{(16}^{20)} have been actively investigated. However, they cause complicated digital logic and
require a long time with a widerange of input to collect sufficient statistical information
for the calibration.
This paper presents a digitaldomain capacitor mismatch calibration scheme in RI SAR
ADC. For verification, a 16bit ADC is implemented in 180 nm CMOS technology, achieving
an SNDR of 87.50dB, an ENOB of 14.24b, and an SFDR of 106.85dB. Section 2 describes
the circuit and algorithm for the calibration. Section 3 shows measurement results,
and Section 4 concludes this work.
Fig. 1. Architecture of the proposed SAR ADC in (a) conversion mode, (b) calibration
mode.
Fig. 2. Circuit configurations in the conversion mode for (a) coarse/find SAR conversion,
(b) residue integration.
II. Circuit Description
1. Architecture
The designed ADC is based on ^{(13)}, operating with two modes, conversion mode and calibration mode (Fig. 1). In the conversion mode, ADC receives the analog input V$_{\mathrm{IN}}$ and quickly
performs 8bit asynchronous SAR conversion, generating coarse 8 MSBs. Then, the residue
integration is performed while receiving V$_{\mathrm{IN}}$. It accumulates the quantization
error by estimating V$_{\mathrm{IN}}$ with the coarse 8 MSBs. After repeating the
integration 2$^{5}$ times, the result is quickly converted again with the same SAR
conversion used in the first step, generating fine 8 bits. During the residue integration
step, a DSM loop simultaneously converts 1bit output (E$_{\mathrm{j}}$) in parallel
at each of 2$^{5}$ integration cycles. It helps to confine the amount of integrated
residue and greatly relieves the requirement of amplifier gain. The total sum of two
SAR conversion outputs and DSM outputs becomes the final digital output. In the summing
process, the 8bit output of the first SAR conversion are scaled up by 2$^{8}$. Since
each DSM output affects the residue with a significance of the 5$^{\mathrm{th}}$ bit
and the residue is then amplified by 2$^{3}$, the DSM output should be scaled by 2$^{8{}5+3}$,
or 2$^{6}$. Detailed circuit operation in the conversion mode is explained in Fig. 2. A DEM is applied to 5 MSB capacitors for averaging. The capacitors for 5 MSBs (C$_{\mathrm{S7:S3}}$)
are implemented in a segmented capacitor array with each capacitance of 32C$_{\mathrm{DEM}}$.
The 31 capacitors of C$_{\mathrm{S7:S3}}$ and a DSM capacitor (C$_{\mathrm{E}}$) form
32 identical capacitors for DEM. The DEM rotates the role of each capacitor during
one full conversion of 32 cycles.
Fig. 3. Simulated INL with amplifier gain of (a) 1024, (b) 512, (c) 256.
The RI with DSM greatly relieves the required openloop amplifier gain. Assuming that
V$_{\mathrm{DD}}$ is the input conversion range, the maximum amplifier output (V$_{\mathrm{o,max}}$)
during RI process confined by DSM operation becomes
Therefore, the maximum nonzero difference at the amplifier input during RI process
due to the finite amplifier gain, A, is
which becomes the inputreferred error at the amplifier input. Since the interstage
closedloop gain for the fine conversion can be reduced by the number of RI cycle
(2$^{5}$), the maximum error at the amplifier output for the fine conversion is calculated
to be
which should be less than 1 LSB of the 8bit fine conversion, or $V_{DD}/2^{8}$. It
leads to the requirement for A, as
Thus, the requirement for the amplifier gain is effectively reduced with factors of
2$^{2}$ and 2$^{5}$ by DSM and RI, respectively. Fig. 3 shows simulated INL for different amplifier gains, revealing the validity of the
analysis.
In the calibration mode, a test input is selfgenerated by applying a known digital
code. For the estimation of capacitor mismatch, two different combinations of digital
codes representing the same amount of test input are prepared. Once the two digital
codes are given, the residue integration is directly processed without the coarse
conversion step. While one digital code provides an equivalent input, the other digital
code performs the role of the coarse MSBs. The result of residue integrations is supposed
to be 0 if the capacitors are perfectly matched. A nonzero residue is then converted
through the subsequent fine SAR operation. Thus, the amount of capacitor mismatch
among the sampling capacitors can be extracted from the ADC output code.
2. Calibration Algorithm
The calibration mode estimates the effect of mismatches of the eight MSB capacitors
used for the input sampling during residue integration. The error is represented in
a form of a ratio with the feedback capacitance ($128C_{LSB}$). Fig. 4 shows how to estimate the capacitance mismatch error. Let the dummy capacitor ($C_{DUMMY}$)
of $4C_{LSB}$ be the reference. The capacitances, $C_{LSB}$, $C_{S0}$, $C_{S1}$, $C_{S2}$
and $C_{DEM}$ are identical if there is no error. To measure each capacitor error,
two given calibration codes (CAL code$_{1}$, CAL code$_{2}$) are applied as the input
and the estimated code for residue integration, respectively. The mismatch between
$4C_{S0}$ and $C_{DUMMY}$ leads to a nonzero residue at the amplifier output after
the first cycle of the residue integration, which is
After the 32nd integration, the output becomes
where $\alpha _{S0}=C_{S0}/C_{LSB}$. The $\alpha _{S0}$ becomes 1, or $V_{o[32]}$
is 0, if there is no mismatch error. Subsequent processing of $V_{o[32]}$ by the fine
AD conversion reveals the information of mismatch error in a form of digital code.
Defining $\varepsilon _{S0}$ to be the mismatch error in the capacitor $C_{S0}$,
Fig. 4. (a) Circuit configurations, (b) code sets for estimation of capacitor mismatch
in the calibration mode.
The mismatch error for $C_{S1}$, represented by $\varepsilon _{S1}$, can be also derived
in a similar way using the previously obtained $\varepsilon _{S0}$. Since the five
MSB capacitors (C$_{\mathrm{S7:S3}}$) and C$_{\mathrm{E}}$ are averaged by DEM, the
mismatch error for those capacitors can be represented by a single parameter with
an averaged error. The capacitance ratios can be obtained as follows:
where $\alpha _{DEM}=C_{DEM}/C_{LSB}$, $\alpha _{S2}=C_{S2}/C_{LSB}$ and $\alpha _{S1}=C_{S1}/C_{LSB}$.
The mismatch errors for capacitors C$_{\mathrm{S1}}$, C$_{\mathrm{S2}}$ and C$_{\mathrm{S7:S3}}$
are represented by $\varepsilon _{S1}$, $\varepsilon _{S2}$ and $\varepsilon _{DEM}$,
respectively. The digitally estimated capacitance ratios ($\alpha _{DEM}$, $\alpha
_{S2}$, $\alpha _{S1}$ and $\alpha _{S0}$) are used in the conversion mode by multiplying
$\alpha _{DEM}$ to D$_{\mathrm{7:3}}$, $\alpha _{S2}$ to D$_{2}$, $\alpha _{S1}$ to
D$_{1}$, $\alpha _{S0}$ to D$_{0}$ and $\alpha _{DEM}$ to E$_{\mathrm{31:0}}$, respectively.
These multiplications can be simply implemented by addition of binaryweighted digitized
errors ($\varepsilon _{S0}$, $\varepsilon _{S1}$, $\varepsilon _{S2}$ and $\varepsilon
_{DEM}$).
To verify the calibration algorithm, we applied random mismatch to DAC which is comprised
of unit capacitors. Fig. 5. shows simulated results when Gaussian statistics are applied to MSB capacitors with
standard deviations of 0.02 and 0.05. The calibration noticeably improves linearity
performance without any missing code. The conventional calibration schemes by only
manipulating the final output code without affecting capacitor DAC could result in
missing codes. However, the proposed calibration is applied to the coarse 8 bits and
DSM bits before the summation with the fine 8 bits. Since the use of DSM provides
a nonzero overlap between coarse 8 bits, there is no missing code in the calibrated
output.
Fig. 5. Simulation results according to MSB capacitor mismatch applied to Gaussian
statistics with standard deviation of (a) 0.02, (b) 0.05.
III. Measurement
The proposed ADC is fabricated using 180nm CMOS technology, occupying a die area
of 0.90 mm x 0.75 mm (0.68 mm$^{2}$). Fig. 6. shows a die photo. The unit capacitance is 20.28fF which is the smallest metalinsulatormetal
(MIM) capacitor with the given technology. Using V$_{\mathrm{DD}}$ as V$_{\mathrm{REF}}$,
a fullscale differential input signal of 3.6V$_{\mathrm{pp}}$ is converted. The chip
provides the outputs of the two SAR conversions and the DSM codes to offchip program,
so that the calibration is verified through software.
Fig. 6. Chip microphotograph.
Fig. 7 shows fast Fourier transform (FFT) spectra with a lowfrequency input. Without the
calibration, SNDR performance is mainly limited by harmonics caused by capacitor mismatches.
However, the calibration improves SNDR by 5.9 dB and SFDR by 14.3 dB, achieving 87.5
dB and 106.85 dB, respectively. It represents an ENOB of 14.24bit. A near Nyquistrate
input shows an insignificant degradation of performance (Fig. 8). The effect of calibration is also seen in code linearity (Fig. 9). There are outstanding repeated 32 patterns in INL and DNL plots before calibration.
It is due to capacitor mismatch between averaged DEM capacitance and other MSB capacitances.
While the peak INL lies within +3.56/3.36 without the calibration, it is improved
to +2.14/2.08 with the calibration. In the whole range of the input frequency, SNDR
and SFDR are improved by calibration (Fig. 10). Table 1 summarizes and compares performance with previously reported SAR ADCs whose resolution
is higher than 12bits. Since the final code is generated through softwarebased calibration,
the total power consumption including digitaldomain code scaling can be only expected
by estimation. This work is continued research of ^{(13)} using the same core blocks. Additional power consumption for digitaldomain code
scaling at the output stage is estimated to be still negligible.
IV. CONCLUSIONS
This work proposes a capacitor mismatch calibration scheme for a residueintegrated
SAR ADC. Unlike the conventional DSMdriven oversampling noiseshaping
Fig. 7. The 65536point FFT spectra calculated from measurement at a lowfrequency
input (a) without calibration, (b) with calibration.
Fig. 8. The 65536point FFT spectra calculated from measurements at a near Nyquistrate
input (a) without calibration, (b) with calibration.
Fig. 9. Measured code linearity (a) without calibration, (b) with calibration at sampling
rate 2 kS/s.
ADC, the proposed ADC does not require any extra postprocessing for decimation or
filtering while performing integration of residue for noise averaging. Matching error
in the binaryweighted inputsampling capacitances is estimated in a form of a digital
number which is used for the scaling of corresponding digital number which is used
for the scaling of corresponding digital code at the output stage during conversion.
A 16bit ADC is implemented using 180nm CMOS technology. The calibration achieves
87.5 dB SNDR and 106.85 dB SFDR, showing improvements of 5.9 dB and 14.3 dB respectively.
Fig. 10. SNDR and SFDR vs. input frequency according to use of calibration at sampling
rate 2 kS/s.
Table 1. Performance Comparison with NyquistRate ADCs

This work

JSSC’ 20 ^{(22)}

IEEE’ 19 ^{(21)}

TCAS’ 19 ^{(5)}

JSSC’ 18 ^{(13)}

VLSI’ 17 ^{(17)}

ISSCC’ 17 ^{(7)}

VLSI’ 16 ^{(9)}

Architecture

SAR

SAR

SAR

SAR

SAR

SAR

pipe. SAR

SAR

Technology [nm]

180

40

180

130

180

55

40

40

Resolution [bits]

16

13

16

12

16

16

14

15

Area [mm2]

0.68

0.005

5.61

0.16

0.68

0.55

0.342

0.32

fs [kS/s]

2

40k

1000

1

2

16k

35k

20

Power Supply [V]

1.8

1.1

5

1

1.8

5/2.5





Power [μW]

8.1*

591

40k

0.11

7.93

10.5k

21.8k

1.17

SFDRNyquist [dB]

106.85

79.2

107.9

78.5

98.2

82

94.3

95.1

SNDRNyquist [dB]

87.5

69

92.3

64.8

84.6

80**

75.1

74.1

FOMs [dB]

168.4*

174.3

166.3

161.4

165.6

165**

164.1

173.4

* : expected
** : with low frequency input
FOMs = SNDR + 10${\cdot}$log(BW/Power)
ACKNOWLEDGMENTS
This work was supported by Engineering Research Center Program of the National Research
Foundation funded by the Korea Ministry of Science and ICT (No. 2019R1A5A1027055).
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Author
received the B.S. degree in electronic and electrical engineering from the Pohang
University of Science and Technology (POSTECH), Pohang, South Korea, in 2014, where
he is currently pursuing the Ph.D. degree.
His current research interests include data converters and lowpower analog circuits.
received the B.S. and Ph. D. degrees in electronic and electrical engineering from
the POSTECH in 2011 and 2017, respectively.
In 2017, he joined Samsung Electronics, Hwaseong, South Korea, where he is currently
a Senior Engineer.
His current research interests include highspeed links, data converters, and analog
circuits for image sensors.
received the B.S., M.S., and Ph.D. degrees in electronic and electrical engineering
from the POSTECH, in 1993, 1995, and 1999, respectively.
From 1999 to 2005, he was a Senior Engineer with Samsung Electronics, South Korea.
From 2003 to 2005, he was a Postdoctoral Researcher with the University of Southern
California, Los Angeles, CA, USA. From 2011 to 2012, he was a Visiting Scholar with
the University of Michigan, Ann Arbor, MI, USA. In 2005, he joined POSTECH, where
he is currently a Professor.
His research interests include highspeed serial/parallel links, frequency generation,
data converters and ultralowpower circuits. Prof. Sim has served on the Technical
Program Committees of the IEEE International SolidState Circuits Conference (ISSCC),
Symposium on VLSI Circuits, and Asian SolidState Circuits Conference (ASSCC).
Since 2019, he has been the director of Scalable Quantum Computer Technology Platform
Center which is an Engineering Research Center nominated by Korea Ministry of Science
and ICT.
He was an IEEE distinguished Lecturer from 2018 to 2019. He was the recipient of the
Special AuthorRecognition Award at ISSCC 2013 and was a corecipient of the Takuo
Sugano Award at ISSCC 2001.
In 2020, he received the Scientist of the Month Award sponsored by Ministry of Science
and ICT of Korea.