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  1. (Dept. of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, Korea)

Electrical stimulator, neural interface, charge balancing, chopped pulse, CMOS


Closed-loop bidirectional neural interface system-on-chips (SoCs) equipped with both electrical stimulation and neural signal recording functions enable a detailed and broad understanding of brain functions and its complex behavior (1-3). Electrical stimulators in these bidirectional systems can treat a variety of neurological disorders by inducing an appropriate neural response with a controlled transfer of charge between the electrode and the target nerve tissue (4).

Among various types of stimulation schemes, the current-mode stimulation has become a popular approach as it does not occupy a large area and can deliver an accurate amount of charge regardless of the impedance fluctuations of the electrode-electrolyte interface. In the current-mode electrical stimulation, there are several important issues to consider. The first issue is the residual potential that accumulates on the electrode-electrolyte interface. During stimulation, residual charges can accumulate on the electrode-electrolyte interface due to the mismatch between the cathodic and anodic pulse and/or irreversible Faradaic reaction, and the voltage difference between the electrodes is generated. This voltage difference known as residual potential can cause damage to the tissue and corrode the electrodes. Generally, the safe range of residual potential that is considered not to damage the tissue is ±50 mV (5,6). Over the past several decades, many charge balancing techniques have been developed to reduce the residual potential for long-term safe stimulation. The advantages and disadvantages of several notable active charge balancing techniques will be described in the later sections. The second issue is the stimulation efficiency. Since only 80 mW/cm2 of heat flux generated by the implanted device can cause irreversible damage to the tissue (7), the stimulator IC which is implanted inside the body requires low power consumption and high efficiency for reliable treatment. Also, as the power consumption of the stimulator is minimized, the life of implanted battery is extended, thereby reducing the number of traumatic re-surgery procedure for battery replacement. On the other hand, if the power is delivered wirelessly through wireless power transfer, less amount of power can be sent or less burden can be placed on the design of power delivery circuits. Thus, several methods have been developed to improve the stimulation efficiency of electrical stimulators. In order to increase the stimulation efficiency, reducing the power consumption through an optimal circuit design and applying various stimulation waveforms have been studied. The stimulation efficiency of the electrical stimulation can be greatly increased if nerve tissue can be activated and neural reactions are induced with less charge injection.

The third issue is the high voltage (HV) compliance required to inject sufficient charge into the target nerve tissue. Since the impedance of the electrode-electrolyte interface can be large depending on the situation, current-mode stimulator circuits require HV compliance to deliver a sufficient amount of charge to the high impedance nerve tissue. In a typical stimulator IC, HV-CMOS or bipolar-CMOS-DMOS (BCD) process is used to meet HV compliance requirements, but it suffers from large chip area, parasitics, and additional costs (8).

In this work, a novel neural stimulator circuit using chopped pulse waveform for efficient stimulation and safe charge balancing is proposed. Transistor stacking technique is utilized to enable standard CMOS devices to be used for output drivers and charge balancer circuits at high supply voltages. To design and electrically verify the proposed stimulator circuit, the electrode-electrolyte interface equivalent model of platinum electrodes used in (7,9) was adopted. Section II briefly discusses some of the waveforms used for electrical stimulation while Section III reviews the conventional charge balancing techniques from previous works. Section IV describes the circuit design of the proposed stimulator system in detail. The experimental results are presented in Section V and the conclusions are given in Section VI.

Fig. 1. Various types of stimulation waveforms (a) Symmetric, (b) Asymmetric, (c) Chopped.



1. Symmetric Biphasic Waveform

In a general electrical stimulation, a symmetric biphasic pulse waveform consisting of a cathodic pulse followed by an anodic pulse is most commonly used. The voltage waveform of a typical biphasic stimulation pulse at the electrode is shown in Fig. 1(a). In the biphasic pulse, the cathodic pulses generate neural spike by initiating the tissue response, and the anodic pulse compensates for the injected charge by flowing the current in the opposite direction for the same period as the cathodic pulse.

2. Asymmetric Biphasic Waveform

In addition to the symmetric biphasic pulse, various stimulation waveforms have been studied to increase the efficiency of electrical stimulation. Fig. 1(b) shows the electrode voltage waveform of an asymmetric biphasic pulse. In the in-vivo experiment in (10), an asymmetric pulse waveform with 100 µs pulse width of cathodic pulse and 200 µs pulse width of anodic pulse was compared to a symmetric pulse waveform with 100 µs of pulse width for both cathodic and anodic pulses. For the asymmetric pulse waveform, the amplitude of anodic pulse was set to half of cathodic pulse. In this experiment, when the asymmetric pulse was used, about 25% higher activation of auditory nerve fibers (ANFs) was maintained with the same stimulation intensity. The authors in (10) estimated that the use of asymmetric pulse waveform compensates for the charge slowly in the anodic phase, resulting in a reduction in the threshold required for nerve activation in comparison to using a symmetric pulse waveform. Therefore, asymmetric pulse waveform can be used to increase the stimulation efficiency. In addition, according to the experiment in (11), the amplitude of the anodic pulse of the symmetric biphasic pulse waveform is equal to cathodic pulse, and this value is larger than the threshold value of nerve tissue activation. This means that unwanted neural reaction can occur by the large amplitude of anodic pulse. Thus, compensating for the injected charge using a small and long anodic pulse that does not exceed the threshold will allow the intended neural response only by cathodic pulses.

3. Chopped Pulse Waveform

There is another stimulation waveform which is a chopped pulse waveform. The voltage waveform of the chopped stimulation pulse is shown in Fig. 1(c). In the in-vivo experiment in (12), the chopped pulse waveform maintained 50% of earthworm’s C-fiber activation with 45% less charge than a conventional unchopped biphasic pulse. According to (12), the stimulation waveform using the short charge injection period provides higher charge efficiency, which is consistent with the charge-duration relationship in (13). In addition, using the appropriate chopped pulse waveform can improve the stimulation selectivity of desired or undesired nerve fibers.

In this work, the proposed stimulator circuit is employs the chopped pulse waveform to improve the efficiency of electrical stimulation. Also, the stimulator circuit is designed to have flexibility by having selectable symmetric waveform and asymmetric waveform options depending on the proper application. In addition, novel charge balancing technique using chopped pulse waveform is proposed.


In this section, some notable features as well as advantages and disadvantages of several charge balancing techniques are described. The general purpose of charge balancing is to minimize the residual potential to ensure long-term safe stimulation.

Electrode shorting is a well-known and representative passive charge balancing technique. This technique is one of the simplest methods for charge balancing, but it has the disadvantage of being unreliable depending on the stimulation frequency and/or impedance fluctuations of the electrode-electrolyte interface (14). Therefore, various active charge balancing techniques have been developed to overcome this disadvantage.

In the active charge balancing scheme, the voltage at the electrode is measured, and the charge is compensated according to the measured polarity and/or value of electrode voltage. Pulse insertion and offset regulation (15,16) techniques are well-known and verified active charge balancing techniques. However, it has a common drawback where complex circuits are required for realization and injecting an additional pulse/DC-offset current for charge balancing increases the power consumption of the stimulator circuit.

In addition to these active charge balancing techniques, there are several other reported charge balancing techniques of adjusting the anodic pulse [9, 17-20] to balance out the residual charge. To induce the desired neural response, the cathodic pulses must deliver the charge to the tissue very accurately. Therefore, since the cathodic pulses should not be altered during the stimulation phase, charge balancing should be performed by controlling the anodic pulses. Stimulating with charge-imbalanced waveform by appropriately adjusting the anodic pulse can reduce the unrecoverable charge in anodic phase, thus minimizing the damage applied to the tissue or metal electrode. Among these charge balancing techniques, the method of controlling the pulse amplitude was proposed in [9, 17, 18], and adjusting the pulse width was introduced in (19,20). However, the circuit proposed in (17) and (19) has a disadvantage of requiring complex digital circuits, and the method proposed in (18) uses a simple digital logic circuit but has a drawback in that it requires an additional current source/sink for charge balancing. The work in (9) also uses simple digital circuitry for active charge balancing with optional electrode shorting, but the overall residual voltage level and the consistency in achieving such residual levels can be further improved. Lastly, the method proposed in (20) uses an additional sensing capacitor, which will limit its usage in multi-channel implementations.


1. Overall Architecture

Fig. 2 shows the block diagram of a typical bidirectional analog front-end in a neural interface system with the proposed stimulator system architecture and the equivalent electrode model used in the design. The equivalent model consists of a double-layer capacitor Cdl representing a non-Faradaic reaction, a resistor RF representing the Faradaic reaction, and a resistor RS representing the nerve tissue. The value of Cdl is 100 nF, RF is 10 MΩ, and RS is 10 kΩ. The stimulator is comprised of a current-steering digital-to-analog converter (DAC), level-shifter, output current driver, and charge balancer circuits. The simple 5-bit current DAC, shown in Fig. 3(a), can control the output stimulation current and uses a cascode topology for good current matching and linearity. The DAC output current is amplified by 10 times by the following output current driver stage to generate the stimulation current. Fig. 3(b) shows the level-shifter circuit which is used to convert the digital control signal level from 0-3.2 V to 9.6-12.8 V, enabling the control for the PMOS switches in the following output current driver. The level-shifter employs the transistor stacked architecture using standard 3.3-V thick gate-oxide devices for safe operation at high voltage. The details on the output current driver and the charge balancing circuits are described in the following subsections.

Fig. 2. Block diagram of the proposed neural stimulator.


Fig. 3. Circuit schematic of (a) 5-bit DAC, (b) level-shifter.


2. Output Current Driver

Fig. 4 shows the schematic of the regulated cascode current mirror and the output current driver used in the proposed stimulator IC. In the regulated cascode current mirror circuit, 1.8-V devices and 3.3-V devices are appropriately used for high output resistance and low voltage headroom. The output current driver employs a bipolar structure to achieve desired voltage compliance with smaller supply voltage than using a monopolar structure. High supply voltage greater than 10 V is required to deliver up to 1 mA of current to 10 kΩ of tissue load. Each switch (SW1-4) is implemented by four stacked 3.3-V transistor devices and no HV devices are used. The stacked devices are biased through the dynamic gate biasing circuit to keep the transient voltage across each terminal within 3.2 V to prevent breakdown due to the high supply voltage. Another advantage of the transistor stacks is that the devices comprising the active charge balancing circuit and the switch devices used for electrode shorting are not directly connected to the electrodes. These switch devices are connected to the drain terminal of the lowermost NMOS stacked device in the output driver instead of being directly connected to the electrode, and thus can be protected from high stimulation voltage. Considering applications where same set of electrodes are used for both stimulation and recording modes in a bidirectional system, a blanking switch is included in the output current driver to be used as a path to the neural recorder inputs. Either the stimulation or recording mode can be selected by controlling the blanking switch. If the blanking switch is turned off, the system goes into stimulation mode and the recording amplifier is disconnected from the electrode. In contrast, when the blanking switch is turned on, stimulation is stopped by the internal logic circuit, and the recording amplifier can be connected to the electrode through the NMOS stacks to record the neural signal. As neural recording circuits are generally operated at low voltage for low-power operation, these circuits also need to be isolated from high voltage. The blanking switch and neural amplifier circuit are not directly connected to the electrode like the charge balancer circuit through transistor stacking technique, so they are all protected from high supply voltage without the need of having a separate isolation switch (8). Although the recording circuits are not discussed in this paper, the stacks and the blanking switch path in the recording mode is designed to cause minimal effect on the noise performance of the neural recording amplifier (21).

Fig. 4. Proposed circuit schematic of output current driver.


3. Chopped Pulse Generation and Active Charge Balancer Circuits

Fig. 5(a) shows the simplified output driver schematic to describe the chopped pulse operation and the charge balancing scheme. The output current driver allows the stimulation current to flow through the electrode to the tissue. Current DAC can generate the output current (IDAC) up to 100 µA with 5-bit resolution. Then the regulated cascode current mirror circuit copies the IDAC at a 1:10 ratio, allowing up to 1 mA of stimulation current to flow. If Φcath and Φcath_bar signals are applied to the waveform selection switches, each switch is turned on and off only during the cathodic phase, respectively. This results in the asymmetric pulse waveform to be generated. On the other hand, if ON and OFF signals are applied to each switch, the copy ratio of current mirror is always maintained at 1:10, and the symmetric stimulation waveform is generated. Fig. 5(b) shows the chopped pulse generation circuit. Chopped pulse control signals (Φcath,chop, Φanod,chop) are generated through logic AND gate and external digital control signals (Φcath, Φanod), and the Φcath,chop signal is applied to the output current driver switch. Fig. 5(c) shows the block diagram of the proposed charge balancer circuit. The charge balancer consists of two analog subtractors, a comparator and additional logic gates. The subtractor and comparator circuits form a differential-difference comparator. The Φanod,chop signal of the chopped pulse generation circuit is not directly applied to the output driver but is inputted to the AND gate of the charge balancer circuit to generate the Φanod,CB signal, and the Φanod,CB signal is applied to the output driver. Fig. 5(d) shows the transistor-level schematic of the designed subtractor circuit. The subtractor circuit contains PMOS tail current transistor and four PMOS input transistors (M1-4). The transistors M2 and M3 are biased by Vb2, and the transistors M1 and M4 measure each electrode voltage indirectly through transistor stacked output current driver. If VS,in+ value is greater than VS,in-, Vout increases. Conversely, if VS,in+ is smaller than VS,in-, Vout decreases.

Fig. 5. Circuit schematic of (a) Simplified output current driver, (b) Chopped pulse generation circuit, (c) Charge balancer circuit, (d) Subtractor circuit.


4. Proposed Charge Balancing Technique

To explain the operation of the charge balancer circuit, the operation of subtractor circuits in Fig. 5(d) is explained first. Since both input nodes of subtractor1 are connected to the GND, M1 and M4 PMOS input devices are turned on strongly. Therefore, due to the bias condition of all input devices, the |VDS| of the tail transistor is increased, and the tail current is maximized by the channel length modulation. At this time, Vout of subtractor1 is fixed to the specific voltage value, and this voltage value is set around 900 mV.

Next, the operation of subtractor2 is explained. The M2 and M3 devices of subtractor2 are biased by Vb2, and M1 and M4 input devices indirectly measure the voltage of each electrode through VS,in+ and VS,in- nodes of the transistor stacking output driver. When the clock signal is HIGH, the chopped stimulation pulses also become HIGH. At this time, the voltage value of VS,in+ and VS,in- increases to a maximum of 3.2 V. This voltage value is large enough to turn off the M1 and M4 devices of subtractor2 regardless of the stimulation current amplitude. Therefore, due to the bias condition of all input devices, tail current is decreased, and the Vout of subtractor2 is fixed to a specific value of 1.2 V. Thus, when the clock signal is HIGH, the output voltage of subtractor2 (1.2 V) is always larger than the subtractor1 output voltage (900 mV) and the output state of the comparator is also always HIGH. As a result, the Φanod,CB signal is continuously generated. The difference between the output voltage values of the two subtractors is set sufficiently large to be around 300 mV to ensure robust operation even with noises or variations in supply voltage or GND. Next, the operation when the clock signal is LOW is explained. When the clock is in LOW state, both chopped pulse control signals Φcathod,chop and Φanod,chop become LOW according to the operation of the chopped pulse generation circuit. Therefore, at the electrodes, only the residual potential is observed, and the M1 and M4 devices of subtractor2 are turned on and measure VS,in+ and VS,in- voltage.

Fig. 6 shows the principle of proposed charge balancing technique and timing diagram of control signals. During the anodic phase, the residual potential of the electrode gradually accumulates from negative to positive value. Depending on the value of residual potential, VS,in+ value decreases from the positive to negative, and VS,in- value gradually increases from negative to positive. Therefore, as the residual potential accumulates on the electrode, the output voltage value of subtractor2 becomes closer to the output voltage value of subtractor1. Finally, when the polarity of residual potential is inverted to positive value, VS,in+ becomes smaller than VS,in-, and the output voltage of subtractor2 becomes lower than the output voltage of subtractor1. Then, comparator output signal changes from HIGH to LOW. Thus, the Φanod,CB signal is kept in the LOW state, and the generation of the additional anodic pulse is stopped. As a result, the residual potential is no longer accumulated on the electrode.

Furthermore, when the comparator output state changes to LOW state, the Φshort signal changes to HIGH and the electrode shorting switch is automatically turned on. As a result, because the electrode shorting is applied when very low residual charge remains due to the proposed active charge balancing technique, residual charge can be removed more quickly and completely. At this time, the pulse width of Φanod only needs to be sufficiently longer than Φcath especially when in asymmetric pulse mode, and even if the Φanod signal is OFF, electrode shorting is maintained until the next Φcath signal is activated. Since the initial value of the residual potential at the time when the electrode shorting is applied is already small, it can overcome the disadvantages of the conventional electrode shorting method.

Fig. 6. Principle of proposed charge balancing and timing diagram.


Fig. 7. Chip micrograph of stimulator IC.



The stimulator IC is designed and fabricated using 0.18-µm standard CMOS process. The micrograph of the implemented chip is shown in Fig. 7, which has an active area of 0.095 mm2. The layout of the entire stimulator IC including the output current driver and level-shifter circuit is designed symmetrically for good matching of stimulation pulses. For linear control of the stimulation current, both the DAC and the current mirror circuits are designed using common-centroid layout including dummy devices. The IC is packaged using chip-on-board method and is soldered on a FR4 printed circuit board (PCB) for verification. The bias voltages and control signals are applied externally to the IC for testing using DC supply and waveform generators. The output stimulation waveform is measured to verify the circuit function and its performances. The equivalent electrode-electrolyte interface model that was described in Section 1 is assembled on the same PCB for measurement. Fig. 8 and 9 show the measured output voltage waveforms of the stimulator, respectively. The stimulation period is set to 1 ms with 100 µs of cathodic phase and 20 µs of interphasic delay. The frequency of the clock signal for generating the chopped pulse is set to 100 kHz with 50% of duty cycle and the unit chopped pulse has 10 µs period. Thanks to the proposed charge balancer operation, the generation of additional anodic pulses stops when the polarity of the residual potential changes from negative to positive in the anodic phase. Also, when the generation of the anodic pulse is stopped, electrode shorting operation is performed automatically, and the positive residual potential that remains already small on the electrode is further quickly discharged to a negligible level. When the stimulator IC is operating in the asymmetric mode, the amplitude of the anodic pulse is set to half of the cathodic pulse through the control of waveform selection switches inside the current mirror circuit, and it has about twice the pulse width. Similar to the symmetric mode, the generation of the chopped anodic pulse stops when the polarity of the residual potential is reversed, and automatic electrode shorting function operates. For all stimulation current amplitudes and stimulation waveforms, the value of the measured electrode residual potential is kept within the safe range of a few millivolts, which far exceeds the requirement of ±50 mV. Fig. 10 shows the measured performance of current DAC. The current DAC circuit controls the stimulation current with 5-bit resolution and achieves high linearity performance with -0.185/+0.137 LSB of DNL and -0.224/+0.492 LSB of INL. Fig. 11 shows the measured voltage compliance of stimulator IC at various DAC codes. At the maximum stimulation current condition, the stimulator IC achieves 12.3 V of voltage compliance at 12.8-V supply. Through optimal circuit design, the stimulator IC shows high linearity of current DAC and high voltage compliance performances. The power efficiency of the stimulator is calculated as Pout/ Pin where Pout is the power delivered to the tissue load and Pin is the total power consumption of stimulator IC. At the 10 kΩ tissue load impedance, Pout is calculated as 10 mW. Compared to the previous work in (9), the sum of static power consumption of the overall stimulator IC at all the voltage supplies is reduced from 0.59 mW to 0.41 mW. Furthermore, the dynamic power consumption of active charge balancer circuit is reduced by half. Thus, the power efficiency of proposed stimulator IC at 20% of stimulation duty ratio is calculated as 50%.

Fig. 8. Measured stimulator output voltage (a) Symmetric pulse mode, (b) Asymmetric pulse mode.


Fig. 9. Measured stimulator output voltage for 4-periods (a) Symmetric pulse mode, (b) Asymmetric pulse mode.


Fig. 10. Measured current DAC performance (a) Stimulation current versus DAC code, (b) Differential nonlinearity (DNL), (c) Integral nonlinearity (INL).


Fig. 11. Measured voltage compliance of stimulator IC.


Table 1 summarizes the performance of the proposed stimulator IC and compares with previous similar stimulator works with charge balancing functions. In this work, a novel active charge balancing technique is proposed and implemented with a simple structure, saving area and power consumption. In comparison to other works, it utilizes the chopped pulse based active charge balancing and automatic electrode shorting to achieve a more complete, consistent, and effective charge balancing to ensure a long-term safe stimulation. In addition, two different types of stimulation waveforms can be selected, providing flexibility according to the application. Finally, HV compliance is achieved using standard CMOS process, providing ease of compatibility for integration with other circuits in a neural interface SoC which may operate at low-voltage. The stimulator IC is implemented on-chip with a small active area of 0.095 mm2 and can be used as a viable solution for multi-channel implementations.

Table 1. Performance summary


This work





Voltage Compliance

12.3 V

12.3 V

< 20 V

< 20 V

10 V


Stimulation Current

1 mA

1 mA

1.2 mA

10 mA

10 mA

Current DAC Resolution








Asym. Chop. Biphasic




Chop. Biphasic




Chopped Pulse based & Automatic Electrode Shorting

Anodic Pulse Modulation & Electrode Shorting

Pulse Insertion

Pulse Insertion

Passive and Offset Regulation

Residual potential after charge balancing

< 3 mV

< 22 mV

< 30 mV


< 20 mV

Power Efficiency


@ 20% stimulation duty ratio


@ 20% stimulation duty ratio



@ 20% stimulation duty ratio




Standard CMOS


Standard CMOS

0.18-µm 24V LDMOS

0.18-µm HV CMOS

0.35-µm HV CMOS


0.095 mm2

0.11 mm2

0.105 mm2

3.36 mm2

(incl. PAD)



A current-mode neural stimulator IC with novel active charge balancing technique using chopped pulse waveform and simple circuitry is proposed and implemented using 0.18-µm standard CMOS process. In the proposed charge balancing method, the number of chopped pulses in the anodic phase is controlled accurately to initially limit the residual potential, then it is followed by an automatic electrode shorting process to further discharge to a negligible level for both symmetric and asymmetric pulse waveform modes. The stimulator employing the proposed charge balancer achieves 12.3 V voltage compliance and get generate up to 1 mA of stimulation current.


This research was funded by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT), (NRF-2018R1C1B6003088). The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC).


Stanslaski S., Afshar P., Cong P., Giftakis J., Stypulkowski P., Carlson D., Linde D., Ullestad D., Avestruz A., Denison T., Jan 2012, Design and validation of a fully implantable, chronic, closed-loop neuromodulation device with concurrent sensing and stimulation, IEEE Trans. Neural systems and rehabilitation engineering, Vol. 20, No. 4, pp. 410-421DOI
Rhew H.-G., Jeong J., Fredenburg J.A., Dodani S., Patil P.G., Flynn M. P., 2014, A fully self-contained logarithmic closed-loop deep brain stimulation SoC with wireless telemetry and wireless power management, IEEE J. Solid-State Circuits, Vol. 49, pp. 213DOI
Liu X., Zhang M., Richardson A. G., Lucas T. H., Van der Spiegel J., 2017, Design of a closed-loop, bidirectional brain machine interface system with energy efficient neural feature extraction and PID control, IEEE Trans. Biomed. Circuits Syst., Vol. 11, pp. 729DOI
Chun H., Yang Y., Lehmann T., Feb 2014, Safety ensuring retinal prosthesis with precise charge balance and low power consumption, IEEE Trans. Biomed. Circuits Syst., Vol. 8, No. 1, pp. 108-118DOI
Ortmanns M., Rocke A., Gehrke M., Tiedtke H.-J., Dec 2007, A 232-channel epiretinal stimulator ASIC, IEEE J. Solid-State Circuits, Vol. 42, No. 12, pp. 2946-2959DOI
Lee H.-M., Park H., Ghovanloo M., Sep 2013, A power-efficient wireless system with adaptive supply control for deep brain stimulation, IEEE J. Solid-State Circuits, Vol. 48, No. 9, pp. 2203-2216DOI
Harrison R. R., Charles C., vol 38, A low-power low-noise CMOS amplifier for neural recording applications, IEEE J. Solid-State CircuitsDOI
Banuaji A., Cha H.-K., Exp Briefs, A 15-V bidirectional ultrasound interface analog front-end IC for medical imaging using standard CMOS technology, IEEE Trans. Circuits Syst. IIDOI
Son J.-Y., Cha H.-K., Jul 2020, An implantable neural stimulator IC with anodic current pulse modulation based active charge balancing, IEEE Access, Vol. 8, pp. 136449-136458DOI
Shepherd R. K., Javel E., Apr 1999, Electrical stimulation of the auditory nerve: II. Effect of stimulus waveshape on single fibre response properties, Hearing Research, Vol. 130, No. 1-2, pp. 171-188DOI
Loizos K., Marc R., Humayun M., Anderson J. R., Jones B. W., Lazzi G., Jun 2018, Increasing electrical stimulation efficacy in degenerated retina: stimulus waveform design in a multiscale computational model, IEEE Trans. Neural Systems and Rehabilitation Engineering, Vol. 26, No. 6, pp. 1111-1120DOI
Qing K. Y., Ward M. P., Irazoqui P. P., Nov 2015, Burst-modulated waveforms optimize electrical stimuli for charge efficiency and fiber selectivity, IEEE Trans. Neural Systems and Rehabilitation Engineering, Vol. 23, No. 6, pp. 936-945DOI
Geddes L. A., Bourland J. D., Jun 1985, The strength-duration curve, IEEE Trans. Biomed. Eng., Vol. BME-32, No. 6, pp. 458-459DOI
Ranjandish R., Shoaei O., 2014, Polarity detection base pulse insertion for active charge balancing in electrical stimulation, 2014 IEEE Conference on Biomedical Engineering and Sciences (IECBES), Kuala Lumpur, pp. 38-41DOI
Yao L., Li P., Je M., 2015, A pulse-width-adaptive active charge balancing circuit with pulse-insertion based residual charge compensation and quantization for electrical stimulation appli-cations, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, pp. 1-4DOI
Sooksood K., Stieglitz T., Ortmanns M., Jun 2010, An active approach for charge balancing in functional electrical stimulation, IEEE Trans. Biomed. Circuits Syst., Vol. 4, No. 3, pp. 162-170DOI
Moradi S., Maghsoudloo E., Lotfi R., Sep 2014, A new approach to design safe and reliable electrical stimulator, Int. J. Biomed. Eng. Technol., Vol. 15, No. 4, pp. 305-316Google Search
Ranjandish R., Schmid A., Oct 2017, An active charge balancing method based on anodic current variation monitoring, in Proc. IEEE Biomed. Circuits Syst. Conf. (BioCAS), Turin, Italy, pp. 1-4DOI
Maghsoudloo E., Rezaei M., Sawan M., Gosselin B., 2016, A new charge balancing scheme for electrical microstimulators based on modulated anodic stimulation pulse width, 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, pp. 2443-2446DOI
Ranjandish R., Shoaei O., Schmid A., 2018, A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation, 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)DOI
Kim H. S., Cha H.-K., Aug 2018, An ultra low-power low-noise neural recording analog front-end IC for implantable devices, IEIE J. Semiconductor Tech. and Sci., Vol. 18, No. 4, pp. 454-460DOI
van Dongen M. N., Serdijn W. A., Feb 2016, A power-efficient multichannel neural stimulator using high-frequency pulsed excitation from an unfiltered dynamic supply, IEEE Trans. Biomed. Circuits Syst., Vol. 10, No. 1, pp. 61-71DOI
Taschwer A., Butz N., Kohler M., Rossbach D., Manoli Y., Dec 2018, A Charge Balanced Neural Stimulator with 3.3 V to 49 V Supply Compliance and Arbitrary Programmable Current Pulse Shapes, in Proc. IEEE Biomedical Circuits Syst. (BIOCAS)DOI


Jin-Young Son

Jin-Young Son received the B.S. and M.S. degrees from the Depart-ment of Electrical and Information Engineering at Seoul National University of Science and Technology (Seoultech), Seoul, Korea, in 2019 and 2021, respectively.

Since 2021, he has been working as an analog IC design engineer at Qualitas Semiconductor, Seoul, Korea.

His research interest includes bidirectional neural interface IC design for implantable biomedical devices.

Hyouk-Kyu Cha

Hyouk-Kyu Cha received the B.S. and Ph.D. degrees in electrical engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003 and 2009, respectively.

From 2009 to 2012, he was a Scientist with the Institute of Microelectronics, (IME), Agency for Science, Technology, and Research (A*STAR), Singapore, where he was involved in the research and development of analog/RF ICs for biomedical applications.

Since 2012, he has been with the Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, Korea, where he is now an Associate Professor.

His research interests include low-power CMOS analog/RF IC and system design for implantable and wearable biomedical devices.