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Title An Electrical Stimulator IC with Chopped Pulse based Active Charge Balancing for Neural Interface Applications
Authors (Jin-Young Son) ; (Hyouk-Kyu Cha)
Page pp.322-333
ISSN 1598-1657
Keywords Electrical stimulator; neural interface; charge balancing; chopped pulse; CMOS
Abstract In this paper, a current-mode neural stimulator integrated circuit (IC) using novel active charge balancing technique is presented. The charge balancing technique proposed in this work is based on chopped pulse waveform, where the number of chopped pulses generated in the anodic phase is controlled accurately in order to limit the amount of residual potential at the electrode. In addition, a quick automatic electrode shorting process follows the active charge balancing phase to further discharge to a negligible residual voltage level in every stimulation cycle, ensuring a safe and long-term operation. Both symmetric and asymmetric stimulation pulse waveforms can be selected to provide wide flexibility for various stimulation environment. The stimulator IC designed using 0.18-μm standard CMOS process achieves 12.3 V of voltage compliance and can deliver 1 mA of maximum stimulation current with 5-bit resolution and high linearity. All circuit functions are integrated on-chip without external components, and the fabricated chip consumes only 0.095 mm2 of active die area.