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  1. (Department of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon-si, Gyeonggi-do 16419, Korea)
  2. (Global Technology Center, Samsung Electronics, Suwon, Gyeonggi-do 16677, Korea)

Transmission line, signal integrity, printed circuit board (PCB), MIPI C-PHY, flexible printed circuit board (FPCB)


Due to the significant increment in data rate requirements, multilevel signal transmissions have attracted attention for improving signal transmission efficiency (1,2). For these requirements, the mobile industry processor interface (MIPI) C-PHY for camera serial interfaces, which has a higher transmission efficiency and a smaller area because it uses an embedded clock, is emerging. In this paper, we propose an interconnect system design guideline consisting of a printed circuit board (PCB) and a flexible printed circuit board (FPCB) that can be used in mobile systems and can efficiently transmit multilevel signals using the C-PHY standard (3,4).

The MIPI C-PHY structure implements a three-phase encode transmission system using three wires per lane (5). At the transmitter side, the transmitted signal is single-ended showed in Fig. 1. At the receiver sides, each two of three signals sending from the transmitter forms an input pair of a differential amplifier. Consequently, the receiver side contains three binary differentials amplifiers which viewed the incoming signal as the differential signal. This signal convention is a critical feature in the C-PHY transmission system that can take advantage of both signaling methods. This differential signaling of the receiver ensures strong immunity to common-mode noise. Furthermore, since the C-PHY method maps 16 bits on seven unique symbols, it has a critical advantage in its wide bandwidth (2.28 Bit/UI) for the current mobile environment. However, as the transmitted signal becomes multilevel, and multiple buses run in parallel, crosstalk among signal lines can affect the signal integrity severely. Hence, the interconnect needs to be designed more carefully ensuring sufficient eye-opening at high frequencies.

Fig. 1. Schematic diagram of the C-PHY transmission.


Many approaches can improve signal integrity at the PCB interconnect design level. In addition to traditional approaches, such as increasing the spacing between the lines and adding a ground guard ring to control crosstalk, ringing, and noise (6,7), many novel design approaches can improve eye-diagrams. Previous research designed an approach to make wide eye-openings such as passive equalizers that cancel negative inter-symbol interference from design optimization (8), common mode filters that suppress common mode noise and differential-to-common mode conversion (9), and split ring resonators that suppress the electric field between the power planes (10).

In mobile systems, the area is a critical design factor. Design methods, therefore, requiring significantly increasing the area are not applicable. Without adding the area overhead, some works relate to modifying the ground plane structure to improve signal integrity. In the previous study, the Electromagnetic Band Gap (EBG) and Defected Ground Structure (DGS) were used to modify the ground plane structure. EBG is a method of creating a stopband to block electromagnetic waves of certain frequency bands by forming periodic patterns (11-13). There are several types of DGSs. One type of DGS is a constructed band stop filter (14-16); an other type of DGS is to improve the transmission bandwidth and reduce crosstalk (17-19).

Fig. 2. The diagram of a MIPI C-PHY signal transmission structure for a mobile system [PCB-FPCB-PCB].


This paper aims to improve the MIPI C-PHY signal, which is a multilevel signaling method, unlike the previous studies that focused on improving the NRZ signal. In the C-PHY signal transmission system of smartphones, the part connecting the transmitters and receivers is not generally composed of a single PCB, but is assembled in the order of PCB-FPCB-PCB, as shown in Fig. 2. We propose a design approach to improve the signal integrity of PCBs without changing the number of layers and the material properties of the stack-up in the conventional C-PHY signal transmission PCB or adding a guard ground. Within these constraints, we focused on modifying the ground plane. In the case of a FPCB, it consists of only two layers, so only a few parts can be changed. It was designed by changing the hole ratio (HR), which is a parameter representing the ratio of the metal area of the mesh ground layer among the two layers. We validate our design through 3D full-wave S-parameter simulation and S-parameter and eye-diagram measurement results of the test structure.

This paper is organized as follows. In Section II, a novel periodic slit ground (PSG) structure for PCBs is proposed to improve eye-opening in multilevel signals. The proposed structure can be applied to a traditional stripline structure without increasing the number of layers or the PCB area. In Section III, we show the FPCB design rule to reduce characteristic impedance fluctuation of a signal line on a mesh ground structure. In Section IV, simulation and measurement results of the fabricated test structure are presented. Section V concludes the paper.


In this section, we propose a novel PCB design approach to improve the signal integrity without increasing the number of layers in a traditional stripline structure or increasing the cross-sectional area by adding guard rings. Fig. 3 and 4 show the cross-sectional and top views of the transmission line using the proposed PSG structure, as compared to the traditional simple stripline structure. The difference of the proposed structure is in the ground planes, which contain periodic slits that are in the same direction with the signal line of finite length repeated at a certain period.

Fig. 3. Cross-sectional view of (a) a stripline structure, (b) a periodic slit structure (PSG).


Fig. 4. Top view of (a) a stripline structure, (b) a periodic slit structure (PSG).


As seen from the top view in Fig. 4(b), the periodic slits in the ground plane are placed below the gap or spacing between the signal lines. This is called a PSG structure. To demonstrate the proposed idea, we designed our structure using a six-layer PCB. The second and fourth layers are ground planes, and the signal lines are arranged on the third layer. The PCB has megtron- $4(\varepsilon r$, $3.83 ; \tan \delta, 0.005$; thickness, $100 \mu \mathrm{m}$ ) as the dielectric material, and a 17.5 ${\mathrm{\mu}}$m thick copper layer. For comparison, the stripline shown in Fig. 3(a) is designed to have a characteristic impedance (Z$_{0}$) of 50 $\Omega$. The width of the signal line is 90 ${\mathrm{\mu}}$m, and the space between the lines is 135 ${\mathrm{\mu}}$m. The PSG structure was designed by modifying the simple stripline structure. Both lines are 10 cm in length. The signal width and spacing are the same as in the stripline, and the periodic slits on the upper and lower ground planes have a width of 50 ${\mathrm{\mu}}$m and a length of 0.9 mm and are repeated in 1 mm periods.

Fig. 5. Dimensions of the stripline structure employing the proposed periodic slit ground structure.


Table 1. Characteristic impedance change due to adding slits





W.o. slits

49.79 $\Omega$

50.16 $\Omega$

50.17 $\Omega$

W. slits

50.14 $\Omega$

50.43 $\Omega$

50.58 $\Omega$





Table 2. Characteristic impedance change due to slit width change

Slit width (µm)












Difference from stripline (%)






Fig. 5 shows the final dimensions of the proposed structure to be used for simulation and test structure fabrication in the following sections. Table 1 summarizes the change of characteristic impedance of three wires, A0, B0, and C0 after adding periodic slits using an ANSYS 2D extractor. The simulation results in Table 2 illustrated that characteristic impedance can be maintained without changing the existing line width or spacing.

The impedance Z$_{0}$ is function of R, L, G, C and frequency described by following formula.

$Z_{0}=~ \sqrt{\frac{R+j\omega L}{G+j\omega C}}~ \cong ~ \sqrt{\frac{L}{C}}$.

Typically, the resistance part (R, G) is negligible in comparison to the reactance part (L, C) so that we will describe the change in impedance according to loop inductance (L) and coupling capacitance (C) variation.

Firstly, all circuits are formed as a closed-loop of conductors and components. And the flowing of charges in this closed-loop forms loop current. The loop inductance (L) is generated by this current and is directly proportional to the loop area. Typically, the current in the closed-loop is formed from the forward current in the conductors and the return current in the reference ground. Hence, the loop area is dependent on the actual current return path in the reference ground. In an ideal ground plane, the return current mostly flows in the area underneath the conductors. Therefore, the loop current flows in the smallest loop area in this case. On the other hand, the return current which flows in the edge of the mesh ground indicates a larger loop area in this case. Consequently, the loop inductance will be higher when using mesh ground instead of the ground plane for the same channel configuration.

Secondly, the capacitance (C) is the total coupling capacitance between conductors and reference ground. In an ideal ground plane, the capacitance directly formed by the overlap area beneath the conductor dominated this capacitance. However, the coupling capacitance is the total fringe capacitance formed by conductors and the grid edges in the mesh ground. Hence, the coupling capacitance is significantly smaller than in the previous case.

In conclusion, the conductor impedance in mesh ground will be higher than the one in the ground plane due to higher loop inductance and smaller coupling capacitance. The simulation results strongly agree with this argument. The simulation results in Table 4 indicate that the channel in high hole ratio (HR) mesh ground needs higher width to achieve the same (50~$\Omega$) impedance. In a high HR mesh ground, the distance between the conductors and the grid edges is large so that the fringe capacitance will decrease and the loop area will increase.

Fig. 6. Simulated S-parameter comparison (a) insertion loss.


The transmission characteristics of the signal line designed on the PCB is confirmed through the S-parameter simulation using the 3D full-wave electromagnetic simulator, HFSS (20).

Fig. 6 shows that the S-parameter characteristics are improved by adding the PSG. The insertion loss is reduced for the high frequency range. The near-end crosstalk and the far-end crosstalk are reduced for the overall frequency range. These improvements in signal transmission and crosstalk are expected to contribute to the improvement of signal integrity of the transmission lines.

Dispersion diagrams are generally used in analyzing electromagnetic bandgap (EBG) structures to find the stopband frequency range (11-13). The dispersion diagram can be obtained from the analytic analysis using transmission line theory or by performing eigenmode simulations of 3D structures using a full-wave simulator. The dispersion diagram shows the relationship between the phase constant (β) and the frequency. For a specific frequency range, if there is no relation between the phase constant and frequency, it means that signals or noise in that frequency band are blocked in that transmission line structure. The dispersion analysis is performed on the unit cell structure defined for the stripline; the PSG structure with the same length as shown in Fig. 7(a). In the stripline structure there exists a relation between phase and frequency for the overall frequency range that we analyzed; however, in the PSG structure there is a stopband region (7.6-9.8 GHz) where there is no relationship between phase and frequency.

Fig. 7. The dispersion diagram analysis (a) unit cell for dispersion analysis, (b) dispersion diagram of a stripline, (c) dispersion diagram of a PSG showing stopband.


The period of the ground slits is defined as the sum of length and spacing between the ground slits in the signal direction as shown in Fig. 4. The period is changed from 1 to 10 mm and the results are shown in Table 3. The period of 1 mm, which is used as the default in our design, shows the best eye-opening. In general, the difference in eye-opening due to the change in period is not large, but as observed, it becomes worse only for the period of 5 mm. This can be explained from the dispersion diagram that we derived from the eigenmode analysis. The dispersion diagrams from different periods are shown in Fig. 8. To block the high frequency noise, there should be a stopband, but for a 5 mm period, there is no stopband compared to other periods.

Table 3. Eye height and width dependence on the period of ground slits

Slit period


EH (mV)

















Fig. 8. The dispersion diagrams of (a) 1 mm and 3 mm periods.


Fig. 9. Parameters of the FPCB design.


Fig. 10. FPCB design flow.



Fig. 9 shows the cross-sectional and top views of the FPCB, which consists of two metal layers, namely, the signal and ground layers. The ground layer is a mesh structure for flexibility. In the signal layer, the line width and space of the three C-PHY single-ended transmission lines (A, B, C) are designed to meet 50 Ω characteristic impedance. Because of the mesh structure on the ground plane, the characteristic impedance estimation based on cross section or 2D approximation does not hold. Therefore, in the FPCB design flow shown in Fig. 10, 3D extracted S-parameters and TDR simulations are used to ensure 50 Ω impedance. While maintaining the 50 Ω characteristic impedance, the variable that can be changed in this structure is the hole ratio (HR) of the mesh ground, which is the ratio of the hole area to the total area defined as $\frac{H S}{H P}$ . We optimized the mesh ground structure by changing HR while keeping the characteristic impedance constant. The HRs of 0.5, 0.66, and 0.75 are compared in Table 4. The signal line length is 20 mm.

Table 4. Characteristic impedance change due to the HR change in the FPCB





















Fig. 11. Circuit simulation schematic for eye-diagram prediction.


The HW is 100 µm in all three cases as shown in Table 4. Because of the mesh ground, the Z$_{0}$ of the FPCB varies along the signal direction. Ranges are shown in Table 4.


We fabricated the PCB-FPCB-PCB structure design shown in Fig. 2. We validated our C-PHY PCB and FPCB design methods by simulating eye-diagrams and measuring the test structure.

1. Simulation Results

Fig. 12. Eye-diagram results from 3D EM and circuit co-simulation.


The simulation setup to obtain the eye-diagram is performed using 3D EM simulation software HFSS from Ansys, and Fig. 11 shows the completed circuit simulation schematic. Fig. 12 shows the eye-diagram when the MIPI C-PHY signal (Vpk−pk, 250 mV; data rate, 2.5 Gsps) is transmitted through the circuit shown in Fig. 11.

These results are with a slit of 50 µm width and 0.1 mm spacing. The results show that the structure using the PSG structure shows significant improvement in eye-opening. Through validation for eye width (EW) and eye height (EH), simulation results with a conventional stripline show 66.24 mV and 0.83 UI, the values with a periodic slit ground are 88.14 mV and 0.91 UI. By adopting the proposed structure, improvement of the eye-opening is achieved by 33.06% in height and 9.63% in width.

2. Measurement Results

Test structures were fabricated and measured to validate the effectiveness of the PSG structure on C-PHY multi-level signal integrity. Two types of PCBs were fabricated to validate the proposed structure and are shown in Fig. 13 below.

First, as shown in Fig. 13(a) with SMA connectors connected at both ends of the transmission lines, is a structure that can be used to measure the S-parameters using the vector network analyzer to see the effect of the PSG on signal transmission and crosstalk. To emulate the mobile signal transmission system, the PCB-FPCB-PCB structure shown in Fig. 2 is fabricated as shown in Fig. 15. Based on the specifications of the actual smartphone, the length of each PCB on both sides is 100 mm, and that of the FPCB in the middle is 20 mm.

Fig. 13. Manufactured PCB (a) SMA connector only structure, (b) SMA connector and narrow pitch connectors (socket).


Fig. 14. FPCB structure with narrow pitch connectors (header) connected.


To construct this structure, the PCB has an SMA on one end and a connector to connect the FPCB on the other end, as shown in Fig. 13(b). The narrow pitch connector (socket) model is the AXE724127 model provided by Panasonic. Fig. 14 shows the FPCB structure connecting the narrow pitch connector (header) at both ends which is the Panasonic AXE824124 model which will be connected to the PCB.

The S-parameters of the PCB structure shown in Fig. 13(a) are measured. Fig. 16 shows the results, insertion loss, near-end crosstalk (NEXT), and far-end crosstalk (FEXT). The trend of the measurement results is consistent with the simulation results presented in Fig. 6.

As shown in Fig. 2, the eye-diagram measurement is performed on the assembled PCB-FPCB-PCB structure described in Fig. 15. One side of the SMA connectors is connected to the MIPI C-PHY signal generator (P339 manufactured by The Moving Pixel Company) for inputting the MIPI C-PHY signal (Vpk−pk, 250 mV; data rate, up to 2.5 Gsps) into the measurement sample. The maximum data rate (2.5 Gsps) of measurement is the highest data rate of the MIPI C-PHY signal generator. The other side of the SMA connectors is connected to an oscilloscope for measuring the eye-opening.

Fig. 15. The assembled structure of the PCB-FPCB-PCB.


Fig. 16. The results from measurement (a) insertion loss, (b) near-end crosstalk, (c) far-end crosstalk.


Because of the effects of coaxial cables and connectors, the eye-openings are deteriorated as compared to the simulation results in the actual measurement, but the same comparison is possible in tendency. Through the measurement results shown in Fig. 17, the EH and EW of the conventional stripline structure are 51.31 mV and 0.22 UI, respectively, and the EH and EW of the PSG structure are 71.11 mV and 0.34 UI, respectively. As shown in Table 5, the signal integrity is improved when the PSG is applied when transmitting the MIPI C-PHY signal with a high data rate.

Fig. 17. Measured eye-diagram of (a) simple stripline structure, (b) PSG.


Table 5. Eye-opening improvement at high data rates

Data rate (Gsps)

EH (mV)


Conventional stripline







Periodic slit ground








In this paper, we proposed a PSG design for PCBs to improve the signal integrity of multilevel single-ended MIPI C-PHY signals near a 2.5 Gsps data rate. The added periodic slits in the upper and lower ground plane of the stripline structures mitigate the coupling between the adjacent signal lines in the multi-bus structure. The PSG scheme reduces crosstalk by decreasing the coupling E-field to the neighboring signal line, which results in a reduction in mutual capacitance and the creation of a stopband in the dispersion diagram. The proposed PSG structure has the advantage of effectively improving the signal integrity characteristics without adding additional layers or changing dimensions or materials.

The effectiveness of the proposed structure is validated through simulation and measurement of a PCB-FPCB-PCB structure that emulates the interconnected system of MIPI C-PHY signal transmission in mobile systems such as smartphones. The 2.5 Gsps data rate condition is the highest data rate defined in the current MIPI C-PHY standard. Simulation results show that at a 2.5 Gsps data rate condition, the PSG structures show improvement in EH and EW by 33.06% and 9.63%, respectively, as compared to the stripline structures. The measurements from the test structures show that at a 2.5 Gsps data rate condition, which is the maximum data rate of the MIPI C-PHY signal generator, the PSG structures show improvement in EH and EW by 38.6% and 9.7%, respectively, as compared to the stripline structures. The proposed idea can be generally applied in PCB designs that will be used in high speed multilevel signal transmissions to improve EH.


This work was supported by the National Research Foundation of Korea grant funded in part by the Korea government (MSIP) (NRF-2020R1A2C1011831) and in part by Samsung Electronics.


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TaeWoong Kim

TaeWoong Kim received B.S. and M.S. degrees in electrical engi-neering from Dongguk University, Seoul, South Korea, in 2006 and 2008 respectively.

He is currently pursuing a Ph.D. degree with the Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea.

He joined the PMIC Design Team of the System LSI division, Samsung Electronics, Hwaseong, South Korea, in 2011 as a Circuit Design Engineer, where he participated in the development of various converter designs, high-speed interface circuits and electromagnetic interference in electronic systems.

YoungBong Han

YoungBong Han received B.S., M.S., and Ph.D degrees in the College of Information and Commu-nication Engineering from Sung-kyunkwan University, Suwon, Korea, in 2015, 2017, and 2020, respectively.

He joined the Memory division, Samsung Electronics, Hwaseong, South Korea, in 2020.

His research interests include signal integrity and electromagnetic interference in electronic systems.

Hung Khac Le

Hung Khac Le received a B.S. degree in Electronic and Communication Engineering from the University of Science and Technology, the University of Da Nang in 2016.

He is currently pursuing M.S. and Ph.D. degrees with the Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea.

His current research interests include power management IC design, high speed I/O design, signal integrity, and electromagnetic compatibility.

JongWan Shim

JongWan Shim received his B.S degree in Electronical engineering from Korea University, Seoul, Korea, in 2005 and an M.S degree in electrical engineering from Sungkyunkwan University, Suwon, Korea, in 2012.

He is currently working for the Global Technology Center of Samsung Electronics.

He has over 10 years of research experience in the fields of SI/PI and EMI. His current research interests include interconnections for high speed serial interfaces, such as connectors, cables, and PCB/FPCBs.

KwangMo Yang

KwangMo Yang received a B.S degree from the College of Electronic Information Technology Engineering from Kwangwoon University, Seoul, Korea, in 2005.

He is currently working for the Global Technology Center of Samsung Electronics.

He has over 10 years of research experience in the fields of EMI and RFI.

His current research interests include interconnections for high speed serial interface, such as connectors, cables, and PCB/FPCBs

BumHee Bae

BumHee Bae received B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2009, 2011, and 2014, respectively.

He worked for KAIST as a Post-Doctoral Fellow in 2015. He is currently with the Global Technology Center of Samsung Electronics.

He has more than ten years of research experience in the field of electromagnetic noise effects on system-level design.

He has authored or co-authored over 50 papers (journal and conference) and has applied or co-applied for over 15 patents.

His current research interests include interconnections for high speed serial interfaces, such as connectors, cables, PCB/FPCBs, and equalizers.

SoYoung Kim

SoYoung Kim received a B.S. degree in Electrical Engineering from Seoul National University in 1997, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1999 and 2004, respectively.

From 2004 to 2008, she worked for Intel Corporation, Santa Clara, CA, and from 2008 to 2009, she worked for Cadence Design Systems.

She is a Professor in the Department of Semiconductor Systems Engineering of the College of Information and Communication Engineering of Sungkyunkwan University.

Her research interests include VLSI computer aided design, signal integrity, power integrity and electromagnetic interference in electronic systems.