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Authors Jin-Fa Lin;Shao-Wei Yu;Chang-Ming Tsai;Ming-Hwa Sheu
Page pp.505-509
ISSN 1598-1657
Keywords Low power; low voltage; flip-flop
Abstract A novel low voltage and low power true-single-phase flip-flop (FF) design is proposed in this paper. It is adapted from conventional Set-Reset latch based FF design and achieves circuit simplification by using virtual VDD scheme. The optimization measure leads to a new design providing better various performances. Based on post layout simulation results using the TSMC CMOS 180 nm technology, the proposed design outperforms the conventional TGFF by 68.7% in energy consumption (at 25% switching activity).