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Authors Min-Kyun Chae;Won-Cheol Lee;Eunsung Seo;Young-Soo Sohn;Kwang-Il Park;Byungsub Kim;Jae-Yoon Sim;Hong-June Park
Page pp.461-469
ISSN 1598-1657
Keywords Tomlinson Harashima precoding; reflective channel; current comparator; 2 UI feedback loop delay constraint
Abstract A half rate Tomlinson Harashima precoding (THP) equalizer for transmitter has been implemented using analog-digital mixed mode circuits to reduce chip area compared to the full digital implementation. The digital multipliers and adders of the full digital implementation are replaced by the current mode DAC with an analog adder, which consists of the superposition of differential pairs with the tail currents corresponding to the impulse responses of the transmission channel. A 3-bit flash ADC converts the output of the current mode DAC with an analog adder to a decision data which is applied back to the DAC through a tapped delay line for 10-tap precoding equalization. 7 current mode comparators are used in the ADC for low kickback noise. The proposed half rate THP equalizer chip in a 65 nm CMOS process works successfully at 5.4 Gb/s with a time margin of 0.24 UI in both a 36-inch FR-4 channel and an 8-inch FR-4 reflective channel with a 4-inch center stub. The chip consumes 87 mW at 1.3 V supply with a chip area of 0.029 mm2. The process-normalized chip area is reduced by 5.7 and 9.8 times compared to the full digital implementation.