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REFERENCES

1 
Kossel M., Dec 2013, A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS, IEEE Journal of Solid-State Circuits, Vol. 48, No. 12, pp. 3268-3284DOI
2 
Yuminaka Y., Mar 2016, Multiple Valued Signaling for High Speed Serial Links Using Tomlinson Harashima Precoding, in IEEE Journal on Emerging and Selected Topics in Circuits and System, Vol. 6, No. 1, pp. 25-33DOI
3 
Kim T., Nov 2016, A Model Predictive Control Equalization Transmitter for Asymmetric Interfaces in 28nm FDSOI, IEEE Asian Solid State Circuits Conference, pp. 237-240DOI
4 
Suleiman A., Feb 2014, Model Predictive Control Equalization for High-Speed I/O Links, IEEE Transaction on Circuits and Systems I: Regular Papers, Vol. 61, No. 2, pp. 371-381DOI