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electrostatic discharge(ESD), LIGBT, Holding voltage, Transient Latch-up, Robustness

## I. INTRODUCTION

In recent years, the demand for high-voltage devices for power IC applications has been increasing. High voltage devices have been used in smart power ICs for switching power supplies and for mobile applications. Electrostatic discharge (ESD) reliability is an important performance requirement for such products (1). Silicon gate-ground NMOS (GGNMOS) and silicon-controlled rectifiers (SCR) are commonly used in ESD protection circuits. Both devices have snapback characteristics due to avalanche breakdown. The GGNMOS has a large area and low current driving capability, which limit its operating frequency and hinder ideal input and output impedance matching. The SCR offers a higher current driving capability and lower silicon footprint than GGNMOS. However, the SCR is vulnerable to latch-up because its structure limits the holding voltage to about 2 V while it has a trigger voltage of about 20 V (2-3). The lateral double diffused MOSFET (LDMOSFET) is widely used as a switching device, as an output driver, and for general ESD protection of high voltage ICs. However, when the LDMOSFET is used for ESD protection, it is fundamentally weak with respect to ESD robustness and ESD reliability. Due to the strong snapback characteristics of LDMOSFETs, the turn-on characteristics of the parasitic bipolar junction transistor is non-uniform. In addition, LDMOS-based ESD protection devices consume a relatively large area of silicon and encounter latch-up problems due to their low holding voltage (4-7).

In this study, a lateral insulated-gate bipolar transistor (LIGBT) was designed and fabricated for 15 V power IC ESD protection. The new LIGBT ESD protection device was designed and fabricated using the 0.18-um BCD (Bipolar-CMOS-DMOS) process. To verify the performance of the proposed device for ESD protection, transmission line pulsing (TLP) was used to measure electrical characteristics while latch-up immunity was evaluated using transient-induced latch-up (TLU) measurements. The robustness of the device to ESD surges was determined by human body model (HBM) and machine model (MM) ESD testing. The measurement results verified the low trigger voltage, high holding voltage, and high ESD robustness of the new LIGBT device. In conclusion, the proposed protection device can be used in 15-V power IC applications.

## II. PROPOSED ESD PROTECTION DEVICE

The cross sections of a conventional LIGBT and the proposed ESD protection device are shown in Fig. 1 and the silicon device footprint for each device is shown in Fig. 2. Unlike a conventional LIGBT, the proposed ESD protection device has a floating N+ diffusion region inside the N-well. The inserted floating N+ diffusion region is an important structure that allows for high holding voltages. Devices with different floating N+ diffusion region lengths (4 um, 6 um, and 8 um) were fabricated resulting in a corresponding change in the base length of the parasitic PNP bipolar transistor. The N+ region is doped higher than the N-well; therefore, electron-hole pairs (EHP) are generated in the floating N+ diffusion region after avalanche breakdown and recombination at the base of the PNP bipolar transistor is increased. Subsequently, the current gain and the base transfer factor are decreased. As a result, the holding voltage is increased.

Fig. 1. Cross sectional view of (a) a conventional LIGBT for ESD protection and (b) a proposed ESD protection devices

Fig. 2. Layout of (a) a conventional LIGBT and (b) a proposed ESD protection device

The mechanism of operation of the proposed protection device is as follows. During normal operation of the internal circuit, the ESD protection device does not operate due to the reverse bias between the P-well and the deep N-well. Accordingly, during normal operation of the internal circuit, the ESD protection device does not affect the operation of the internal circuit. However, when an ESD surge injects current into the P+ collector region, punch-through occurs and current is directed towards the emitter due to depletion layer diffusion because of the reverse bias between the P-well and deep N-well. The electrons and holes produced during this process exit via the collector and emitter, respectively. The hole current formed induces a potential buildup across the P-well. When it exceeds the potential barrier between the P-well and the emitter N+, the P-well and emitter N+ are forward biased and the parasitic NPN bipolar transistor formed by the emitter N+, P-well, and deep-N-well is turned on. Since the parasitic NPN bipolar transistor provides the base current for the parasitic PNP bipolar transistor formed by the collector P+, deep N-well and P-well, the result is that the parasitic NPN/PNP bipolar transistors form an ESD current discharge path via positive feedback. Such process is the same for conventional LIGBTs. However, the base current for the parasitic PNP bipolar transistor is increased by the heavily doped N+ floating diffusion region (L1) inside the N-well. Increasing L1 increases the base length of the parasitic PNP bipolar transistor therefore decreasing the current gain and increasing the holding voltage.

## III. EXPERIMENTAL RESULTS

### 1. TLP Measurement

The proposed protection device was fabricated using the 0.18-um BCD process. The basic electrical characteristics were measured by TLP and are typically presented as a plot of the current versus the voltage (I-V), showing the turn-on point parameter (Vt1, It1) of the snapback protection structure. In addition, the TLP I-V curve can easily reveal the on-resistance and the second breakdown current (8). The changes in holding voltage according to the length of the floating N+ diffusion region were measured. In order to further verify the changes in holding voltage due to the reduced current gain of the parasitic PNP bipolar transistor produced from the floating N+ diffusion region, the changes in the holding voltage were measured by increasing the floating N+ diffusion region by varying the base width, which affects the current gain in fixed conditions. Fig. 3 shows the I-V characteristics of the three most common ESD protection devices. Since the SCR has a low holding voltage of 1.5 V, latch-up problems can occur. The GGNMOS has low trigger and holding voltages, therefore, it is not suitable for high-voltage protection. On the other hand, the LIGBT can handle ESD currents effectively by operating two bipolar transistors like the SCR. Moreover, the LIGBT also operates at relatively high voltages and it can be used for higher voltage applications compared to the GGNMOS and the SCR. Fig. 4 shows the TLP I-V graph for the proposed protection device with respect to the floating N+ diffusion region L1 parameter varying from 0 um (conventional) to 4 um, 6 um, and 8 um.

Fig. 3. TLP characteristics of conventional structures (SCR, GGNMOS and LIGBT)

Fig. 4. TLP characteristics of proposed protection device with respect to the L1 parameter

Fig. 5. Respect to the L1 parameter of Triggering voltage, Holding voltage and Second breakdown current.

The measurement results showed that as width of the floating N+ diffusion region was increased from 0 um to 4 um, 6 um, and 8 um, the trigger voltage was 19.1 V, 19.4 V, 19.6 V, and 20.2 V, respectively. This shows a trigger voltage spread of approximately 1.1 V, which is almost no change. However, it can be observed that the holding voltage was 7.5 V, 8.7 V, 14.7 V, and 16.2 V, respectively, with wide increments. Fig. 5 shows the electrical characteristics (trigger voltage, holding voltage, second breakdown current) with respect to the changes in the floating N+ diffusion region. In Fig. 5, it can be observed that the second breakdown current decreases as the L1 variation. This is due to the increase in the holding voltage significantly increasing the internal resistance of the protection device. When the protection device internal resistance increases, self-heating of the device occurs during ESD current discharge, resulting in severe thermal damage of the device. Accordingly, the second breakdown current decreases as L1.

### 2. Transient Latch-up Test

In order to accurately test for latch-up immunity, the transient-induced latch-up (TLU) was measured. Fig. 6 shows the typical TLU measurement set-up (9). To test the LIGBT ESD protection device (DUT), anode and cathode terminals were fabricated. An ESD pulse was simulated by using a capacitor charged with constant voltage connected to the anode of the DUT as shown in Fig. 6. At the same time, the power supply that is set up for supplying DC voltage to the internal circuit is connected to the same node (node X). The ESD protection device operates if the charging voltage is applied (ESD pulse reproduced) to the capacitor through switch 1 (S1).

Fig. 6. The measurement setup for transient latch-up(TLU) test.

Here, measurements were taken by a voltage probe at node X. In addition, latch-up can be determined from changes in the DC voltage level due to the operation of the ESD protection device after the simulated ESD pulse. Fig. 7 shows the voltage waveforms obtained from TLU measurements. The results show that the holding voltages for N+ diffusion region lengths of 0 um and 4 um were 7.5 V and 8.7 V respectively, below the set-up DC power supply of 15 V. These results indicate that latch-up has occurred. It can be observed from Fig. 7(a) and (b) that the level of the DC voltage changed after ESD protection device was triggered. The device with a 6 um N+ diffusion region was also tested and a holding voltage of 14.7 V was measured. While this was close to supplied voltage of 15 V, it was also verified that latch-up occurred. In contrast, for the device with an 8 um N+ floating region, the holding voltage was 16.2 V, higher than the 15 V DC power supply, and it was observed that the supplied voltage returned to 15 V after the operation of the ESD protection device.

Fig. 7. The measured TLU voltage waveforms (a) 0 um N+ floating region occurs latch-up(fail) (b) 4 um N+ floating region occurs latch-up(fail) (c) 8 um N+ floating region passes latch-up.

Fig. 7(c) shows that the DC voltage returns to the level prior to the operation of the ESD protection device. Accordingly, the test results verify that the device has latch-up immunity. Therefore, it has been confirmed through measurements that the protection device with an N+ floating region 8 um in length can be used for the ESD protection of integrated circuits that have a 15 V power supply.

### 3. ESD Robustness

Table 1. ESD Characteristics of proposed protection device with respect to L1 parameters

 4 um 6 um 8 um TLP test Vt1 (V) 19.4 19.6 20.2 Vh (V) 8.7 14.7 16.2 It2 (A) 7.5 7 4.6 ESD robustness HBM (kV) 8 8 6 MM (V) 800 800 550 Occurrence of TLU Failure Failure Pass

To evaluate the ESD sensitivity of the proposed protection device, HBM and MM pulses were applied to the device using an electrostatic discharge simulator (ESS-6008, NoiseKen Laboratory Co.) and any leakage current and changes in the DC I-V waveforms were monitored using a 370A curve tracer (Tektronix) in order to check for any device damage. The ESD robustness tests show that when the floating N+ diffusion region was 4} \textnormal{um} \textnormal{and 6} \textnormal{um}\textnormal{, the HBM protection voltage level was 8 KV and the MM protection voltage level was 800 V (maximum measurement range) while when the floating N+ diffusion region was 8 um, the HBM protection level was 6 kV and the MM protection level was 550 V (Table 1). It can be observed that the proposed protection device exceeds the commercial standard for ESD robustness (HBM=2 kV, MM=200V).

### 4. Temperature Characteristics

The effect of device temperature on trigger and holding voltages of the proposed protection device with L1=8 um was analyzed using the TLP measuring system and a hot-chuck controller. The high temperature characteristics are important because they affect the electrical characteristics, specially It2, of the ESD protection device (10-11). When the temperature of the proposed protection device was increased from 300K to 500K, the holding voltage decreased from 16.2 V to 13.5 V. Such decrease in the holding voltage is due to the decreased VBE (emitter-based voltage) of the parasitic NPN/PNP bipolar transistor at high temperatures. When the temperature increases, the diode current increases, leading to reduced VBE. The temperature dependence of the diode saturation current, which is an important factor in ESD operation, can be expressed by the following set of equations:

##### (1)
$$V_{T}=I_{t}\left(R_{n}+R_{p}\right)+V_{BEon}+V_{dsB}$$ $$V_{H}=V_{BEon}+V_{BCQ1}$$ $$I_{H}=\frac{V_{BEon}}{\beta _{npn}\beta _{pnp}-1}[\frac{1}{Rn}\left(\beta _{pnp}+1\right)\beta _{npn}+\frac{1}{Rp}\left(\beta _{npn}+1\right)\beta _{pnp}]$$

In Equation (1) above, as the temperature increases, VBE decreases and the holding voltage also decreases. As the carrier mobility of silicon decreases at high temperatures, its resistivity increases. Thus, the N-well resistance (RNW) and the P-well resistance (RPW) also increase as the temperature increases.

Table 2. Electrical characteristic of the proposed ESD protection device at high temperature (300 to 500 K, L1=8um)

 Temperature Trigger Voltage ($V_T$) Holding Voltage ($V_H$) $2^{nd}$ breakdown Current ($I_{T2}$) HBM 300K 20.2 V 16.2 V 4.6 A 6 kV 350K 19.8 V 15.7 V 4.4 A 6 kV 400K 18.7 V 15.2 V 4.1 A 5 kV 450K 17.5 V 14.2 V 3.3 A 4 kV 500K 16.4 V 13.5 V 3.1 A 4 kV

Silicon-based ESD protection devices have a 10-20% holding voltage reduction at 500k due to degradation losses (12-13). According to the measurement results, the proposed ESD protection device has a robustness of HBM 5kV at 400K and a holding voltage higher than the operating voltage. At a temperature of 500K, the holding voltage of the proposed ESD protection device is reduced by 16% compared to 300K.

## V. CONCLUSIONS

In this study, an LIGBT-based ESD protection device was designed and fabricated. The proposed protection device was fabricated using a Dongbu 0.18-um BCD semiconductor process. The I-V characteristics and ESD robustness of the device were evaluated using TLP and TLU tests. The effect of temperature on trigger and holding voltages was also characterized. In the new ESD protection device, the holding voltage was increased by inserting a floating N+ diffusion region into the N-well of a conventional LIGBT structure. The results show that when the length of the floating N+ diffusion region was varied from 4 um, 6 um, and 8 um, the holding voltages were 8.7 V, 14.7 V and 16.2 V, respectively. It was verified by the TLU test that the device achieves excellent latch-up immunity when the floating N+ diffusion region is 8 um. In addition, the ESD robustness measurements show that the HBM protection level was 8 kV and the MM protection level was 800 V when the floating N+ diffusion region was 4 um and 6 um, while the HBM protection level was 6 kV and the MM protection level was 550 V when the floating N+ diffusion region was 8 um. Therefore, the new LIGBT-based ESD protection device with a floating N+ diffusion region of 8 um can be used for 15 V power IC applications.

### ACKNOWLEDGMENTS

This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information Technology Research Center) support program(IITP- 2019-2018-0-01421) supervised by the IITP(Institute of Information & communications Technology Planning & Evaluation) and by the Ministry of Trade, Industry & Energy (10065137, “Boosted Class-DG Audio Power Amplifier with Embedded ADC for Mobile Speaker Protection.

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## Author

##### Kyoung-Il Do

Kyoung-Il Do was born in Seoul, Republic of Korea, in 1989.

He was M.S and PhD.-course since 2016 in Electronics and Electrical Engineering, Dankook University.

His current research interests include electrostatic discharge (ESD) protection circuit design and semiconductor devices, such as power BJTs, LDMOSs, and IGBTs; and electrostatic discharge (ESD) protection circuit design.

##### Byung-Seok Lee

Byung-Seok Lee received the B.S. degree in the Department of Electronics Engineering from Seokyeong University, Korea, in 2010 and M.S. degree in Electronics and Electrical Engineering from Dankook University, Korea, in 2012.

He is currently pursuing the Ph.D. degree in the Department of Electronics and Electrical Engineering from Dankook University, Korea.

His interests include ESD Protection Circuit, Power Device.

##### Yong-Seo Koo

Yong-Seo Koo was born in Seoul, Republic of Korea, in 1957.

He received his B.S., M.S. and Ph.D. in Electronic Engineering from Sogang University, Seoul, Republic of Korea, in 1981, 1983 and 1992, respectively.

He joined the Department of Electronics and Electrical Engineering, Dankook University as a Professor, in 2009.

His current research interests include semiconductor devices, such as power BJTs, LDMOSs, and IGBTs; high-efficiency power management integrated circuits (PMICs), such as DC-DC converters; and electrostatic discharge (ESD) protection circuit design.