https://doi.org/10.5573/JSTS.2026.26.2.91

(Nak Hyeon Kim) ; (Min-Jeoung Kim) ; (Ho-Young Cha)

The formation of reliable p-type ohmic contacts remains a key challenge in GaN device technology. In this work, Mg incorporation pretreatment was employed to improve p-type GaN ohmic contacts, with the optimum annealing temperature identified as 550 ?C for both Ni/Au and Pd/Ni/Au stacks. Secondary ion mass spectrometry (SIMS) confirmed enhanced Mg incorporation near the surface after annealing. Despite improved ohmic formation, the contacts exhibited non-ideal rectifying behavior, showing that contact resistance cannot be treated as a constant value or simply extracted from conventional TLM analysis. Instead, it must be considered as a current-dependent parameter. The influence of the non-ideal contact behavior on device performance was quantitatively analyzed using vertical PN diodes, showing that contact resistance accounted for a significant fraction of the total on-resistance at high current densities. These results highlight the need for current-dependent resistance models to enable accurate design and performance prediction of GaN-based devices.

https://doi.org/10.5573/JSTS.2026.26.2.97

(Eun Pyo Hong) ; (Sang Won Yoon)

Three-dimensional (3D) High Bandwidth Memory (HBM) packages suffer from limited heat removal through the low thermal conductivity epoxy molding compound (EMC). Heat from the logic die is forced to traverse only through the stacked DRAM dies, which elevates the logic die temperature and corner stress. We propose a hollow rectangular copper structure named a plugged sidewall, embedded in the mold region surrounding the DRAM stack. This structure forms high thermal conductivity heat dissipation paths and provides mechanical constraint. Through 3D finite element analysis (FEA) simulation across 4-dies, 8-dies, 12-dies, and 16-dies stack configurations, we verified the effectiveness of the proposed structure. The proposed package design lowered the maximum package temperature by more than 13% for all stack heights compared to the conventional structures, effectively alleviating thermal hotspots formed at the logic die. Heat flux analysis showed that heat from the logic die was diverted to the sidewall embedded in the EMC region, indicating that previously nonexistent heat dissipation path within the EMC region was created by the new structure. In addition, the average thermal stress at the four corners of the logic die decreased more than 32% for all cases. Simulation results conforms that our proposed design offers a practical path to improve heat dissipation and robustly expands thermal headroom while mitigating corner-dominated thermal stress for high-stacked 3D HBM packages.

https://doi.org/10.5573/JSTS.2026.26.2.106

(Yu-Bin Kim) ; (Sung-Ho Kim) ; (Dong-Min Kim) ; (Chae-Min Yeom) ; (Shivam Kumar Guatam) ; (Yong-Goo Kim) ; (Hyuk-Min Kwon) ; (Hi-Deok Lee)

This study investigates effect of the top electrode material on the resistive switching and synaptic properties of HfO2/ZnO-based memristive devices. By varying the TE materials (Pd, Ti, TiN, and TiAu), we analyzed influence of the work function difference between top and bottom electrodes on electrical performance. Devices with a larger work function difference exhibited lower forming and set voltages, which is attributed to the enhanced internal electric field. Despite this, all of the devices showed similar conduction mechanisms, with the Ti device demonstrating gradual reset behavior due to its low Gibbs free energy. Synaptic characteristics including long-term potentiation (LTP) and long-term depression (LTD) were evaluated using a pulse scheme, that confirmed stable analog conductance modulation. These results suggest that selecting an appropriate TE material can improve switching efficiency as well as synaptic reliability of the memristive devices.

https://doi.org/10.5573/JSTS.2026.26.2.114

(Seunghun Yi) ; (Seonghearn Lee)

To directly extract the model parameters of the physical off-state small-signal equivalent circuit of bodycontact PD-SOI MOSFETs, novel extraction equations are derived from Y-parameter equations approximated in both low and high-frequency regions. Unlike conventional direct extraction methods that require additional test patterns or measurements under varying bias conditions, the proposed technique enables direct extraction of all off-state equivalent circuit parameters using only a single S-parameter measurement, making it much simpler. The off-state model built with this novel extraction method shows excellent agreement with measured S-parameters in the wide bias range and the frequency range from 100 MHz to 40 GHz.

https://doi.org/10.5573/JSTS.2026.26.2.121

(Shihun Lee) ; (Gihong Park) ; (Suk-Kang Sung) ; (Yoon Kim)

In this study, we propose a novel Inter-Deck-Body (IDB) architecture to enhance the erase operation performance of 3D NAND flash memory. The IDB architecture is positioned between adjacent decks and consists of a P + IDB region, an N+ channel connector, and four IDB dummy cells. During the erase operation, holes are directly supplied from the P+ IDB region to the channel, thereby boosting the channel potential. Unlike conventional 3D NAND flash memories that rely on gate-induced drain leakage (GIDL) for erase operation, the proposed architecture achieves erase without inducing GIDL current. Technology computer-aided design (TCAD) simulations were conducted to verify the functionality of the proposed IDB structure. Through these simulations, optimal structural parameters and biasing conditions for each operation mode were identified. In particular, it was demonstrated that the IDB-based erase scheme exhibits superior erase efficiency compared to conventional GIDL-based erase methods. Moreover, the proposed architecture ensures read operation without degradation in on-current, maintaining high read performance. These results indicate that the proposed IDB architecture is a highly scalable and promising solution for multi-deck 3D NAND flash memory, offering both improved erase performance and read integrity.

https://doi.org/10.5573/JSTS.2026.26.2.130

(HyunJoon Jeong) ; (Junha Suk) ; (Jeong-Taek Kong) ; (SoYoung Kim)

Standard cell performance and timing optimization becomes increasingly challenging in advanced technology nodes such as sub-3 nm nanosheet FET (NSFET) with buried power rails (BPRs). In this paper, we propose a novel standard cell optimization methodology based on machine learning (ML) that simultaneously achieves performance improvement and timing balance while reducing simulation overhead. For INV/NAND2/NOR2 cell layouts designed with 3 nm NSFETs, we perform post-layout simulations using parasitic component extraction (PEX) to compute delays and power and generate a dataset. Using this dataset, we train an artificial neural network (ANN) model as an objective function and perform multi-objective Bayesian optimization (MOBO) under explicit design rules and cell height constraints to achieve 1:1 rise-fall delay symmetry across the cells. Within this framework, high performance (HP) applications target minimum propagation delay with 1:1 symmetry, while low power (LP) applications target minimum total power with the same symmetry. For 3 nm and beyond NSFET technology, delay is reduced by up to 23.2% for HP INV cells, and power is reduced by 10.3% for LP NAND2 cells. For NAND2/NOR2 cells, the rise-fall delay balance is improved by more than 15%. To evaluate the performance of the optimized standard cells, a 7-stage ring oscillator (RO) and a 4-bit ripple carry adder (RCA) were used as test circuits. The results show significant improvements in both delay and power efficiency.

https://doi.org/10.5573/JSTS.2026.26.2.141

(Yekwang Choi) ; (Youngsik Kim) ; (Shinwoong Kim)

This paper presents a 7.6-GHz fractional-N digital phase-locked loop (DPLL) incorporating a timeamplifier (TA) based time-to-digital converter (TDC). The TA amplifies the phase residue and re-samples the loop counter, enabling fine time-to-digital conversion without significant hardware overhead. Because the TDC operates by counting the digitally controlled oscillator (DCO), its resolution automatically scales with the DCO period, eliminating the need for explicit gain matching, while an analog calibration compensates TA gain variation for robust PVT performance. For high-frequency capability, a latch-based counter is introduced, overcoming the operatingspeed limitation of conventional synchronous counters. The PLL is implemented in 28-nm CMOS, the design occupies 0.027 mm2 , consumes 8.39 mW, and demonstrates ±0.5-LSB INL/DNL based on post-layout simulations, achieving 692-fs rms jitter at 7.693 GHz.

https://doi.org/10.5573/JSTS.2026.26.2.150

(Min-Ju Lee) ; (Seong-Ho Kim) ; (Ga-Hyun Shin) ; (Jae-Sung Park) ; (Woo Young Choi) ; (Il Hwan Cho)

In the pursuit of high-performance and high-density memory solutions for modern data-centric applications, capacitor-less one-transistor dynamic random-access memory (1T DRAM) has emerged as a promising alternative to conventional one transistor one capacitor dynamic random access memory (1T1C DRAM) structures. This study proposes a silicon-based ternary 1T DRAM device that integrates the structural simplicity of capacitor-less 1T DRAM with the enhanced data-storage efficiency of ternary logic, enabling each cell to represent three distinct states (0, 1, and 2). Different from the carbon-nanotube-FET (CNTFET)-based ternary devices, which face significant challenges in manufacturability and process integration, the proposed device leverages standard silicon-on-insulator (SOI) MOSFET technology, ensuring compatibility with existing complementary metaloxide-semiconductor (CMOS) fabrication processes. Through TCAD Sentaurus simulations, we demonstrate the feasibility of the proposed architecture, validating clear state separation during write, read, and hold operations by controlling the number of electrons stored in quantum wells. Furthermore, the device exhibits excellent thermal stability up to 373 K, maintaining robust current ratios and retention characteristics. This work provides a practical and scalable pathway toward ternary-memory implementation, contributing to the development of next-generation memory systems with improved integration density and energy efficiency.

https://doi.org/10.5573/JSTS.2026.26.2.159

(Jinman Myung) ; (Geonwoo Park) ; (Ho Kim) ; (Suyeon Lee) ; (Ilku Nam)

A 5G millimeter-wave n257 band CMOS down-conversion mixer using inner-diameter-shared source degeneration inductors with magnetic coupling effect is proposed for 5G wireless communication systems. Considering the coupling coefficient of these inductors, the derivative superposition linearization technique is applied to the proposed mixer to improve its linearity. The 28- GHz down-conversion mixer with a local oscillator was implemented using a 65-nm RF CMOS process. The down-conversion mixer draws 11.7-mA current from a 1-V supply voltage. It achieves a conversion gain of 11.8 dB, noise figure of 9.74 dB, and a third-order input intercept point of 7 dBm.

https://doi.org/10.5573/JSTS.2026.26.2.167

(Ah-Hyun Hong) ; (Hyungjun Choi) ; (Kyeungbin Kim) ; (Dong-Wook Park)

Flexible organic thin-film transistors (OTFTs) offer intrinsic mechanical flexibility, low-temperature process compatibility, and large-area manufacturability, making them attractive platforms for next-generation wearable and conformable electronics. In this study, we compared single-gate (SG) and double-gate (DG) structures in poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT) channel-based flexible OTFTs and demonstrated the superiority of the DG structure in terms of mechanical and electrical stability, as well as long-term durability under constant electrical and mechanical stress conditions. In DG devices, the operation was controlled by the gate-bias configuration, enabling top-gate (TG), bottom-gate (BG), and double-gate (DG) operation. Under DG operation, the on/off ratio was approximately 50× higher than that under BG operation and ∼ 10× higher than that under TG operation, and the field-effect mobility was increased by ∼ 30× and ∼ 3×, respectively. The DG mode also exhibited the lowest subthreshold swing (SS) among the three modes. Because DG transistors use two gates to modulate the channel, they showed smaller variations in threshold voltage (Vth) and on-current under bending/curved conditions, compared to SG devices. These results indicate that the DG structure may help preserve device characteristics against mechanical and electrical stress. Furthermore, the DG devices exhibited tunable modulation of the drain current and Vth via gate-biasing, suggesting their potential for flexible electronic applications requiring controllable operation under mechanical bending. Overall, these results demonstrate that the DG structure is a robust design strategy for high-performance flexible OTFTs and offers practical guidelines for mechanically reliable organic electronics.

https://doi.org/10.5573/JSTS.2026.26.2.174

(Myungchul Yoon)

An implementation of bit-serial bitonic sorting network (BBSN) is presented in this paper. While all bits of an input enter sorting network simultaneously, inputs to bit-serial sorting network enter as bit-streams. BBSN uses 1-bit compare and swap (CAS) unit while normal bitonic sorting networks (NBSN) use multi-bit CAS units. By using a small and fast CAS unit, BBSN can reduce area, power consumption, and latency of NBSN. The size of the BBSN is about 81% of NBSN for 8-bit 8 inputs, and it is about 20% for 8-bit 128 inputs. For 16-bit inputs, it is 17% for 128 inputs. Comparing power consumption of BBSN to NBSN, it consumes 60% of NBSN for 128 of 8-bit inputs, and 40% for 16-bit inputs. The proposed sorting network could be slower than NBSN for small number (N < 32) of wide-bit (m ≥ 16) inputs, but it becomes faster when number of input increases. BBSN is 16% faster than NBSN in sorting 128 of 16-bit inputs, and the percentage grows as the number of inputs increases. The proposed sorting network could be used for many applications which require high-speed sorting operations.