Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2026-04 (Vol.26 No.02)
  4. 10.5573/JSTS.2026.26.2.121
XML PDF INFO REF

REFERENCES

1 
Choi J. D. , 2023, Proceedings of the Flash Memory SummitGoogle Search
2 
Park S.-S. , Lyu J.-D. , Kim M. , 2025, 30.1 A 28Gb/mm2 4XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs, Proc. of the 2025 IEEE International Solid-State Circuits ConferenceDOI
3 
Caillat C. , Beaman K. , Bicksler A. , 2017, 3DNAND GIDL-assisted body biasing for erase enabling CMOS under array architecture, Proc. of the 2017 IEEE International Memory WorkshopDOI
4 
Yoo H.-N. , Yang Y. , Park M.-K. , Choi W. Y. , Lee J.-H. , 2023, Analysis of GIDL erase characteristics in vertical NAND flash memory, Journal of Semiconductor Technology and Science, Vol. 23, pp. 196-201DOI
5 
Kang J.-K. , Lee J. , Yim Y. , 2021, Highly reliable cell characteristics with CSOB (Channel-hole Sidewall ONO Butting) scheme for 7th generation 3D-NAND, Proc. of the 2021 IEEE International Electron Devices Meeting, pp. 10.1.1-10.1.4DOI
6 
Goda A. , 2021, Recent progress on 3D NAND flash technologies, Electronics, Vol. 10, No. 24DOI
7 
Kim Y. , Kim S. , 2023, Simulation acceleration of bit error rate prediction and yield optimization of 3D V-NAND flash memory, IEEE Access, Vol. 11, pp. 93956-93967DOI
8 
Shim S. I. , Jang J. , Song J. , 2023, Trends and future challenges of 3D NAND flash memory, Proc. of the 2023 IEEE International Memory WorkshopDOI
9 
Park S. , 2021, Highly reliable cell characteristics with 128-layer single-stack 3D-NAND flash memory, Proc. of the 2021 Symposium on VLSI TechnologyGoogle Search
10 
Lim S. , Kim S. , Lee C. , 2023, Improvement of GIDL-assisted erase by using surrounded BL PAD structure for VNAND, Proc. of the 2023 IEEE International Memory WorkshopDOI
11 
Jung D.-H. , Lee K.-S. , Park J.-Y. , 2021, Demonstration of multi-layered macaroni filler for back-biasing-assisted erasing configuration in 3D V-NAND, Journal of Semiconductor Technology and Science, Vol. 21, pp. 334-339DOI
12 
Choi S. , Choi C. , Jeong J. K. , Song Y.-H. , 2022, Innovative structure to improve erase speed in 3-D NAND flash memory with cell-on-peri applied, IEEE Transactions on Electron Devices, Vol. 69, pp. 4883-4888DOI
13 
Lee G.-H. , Kim K.-R. , Yang H. J. , Park S.-K. , Cho G.-S. , Choi E.-S. , Song Y.-H. , 2012, Investigation of vertical channel architecture for bulk erase operation in three-dimensional NAND flash memory, Japanese Journal of Applied Physics, Vol. 51DOI
14 
Kim D. , Shim W. , 2025, SiGe-surrounded bitline structure for enhancing 3D NAND flash erase speed, Applied Sciences, Vol. 15, No. 13DOI
15 
Han J. , Kang S. , Kim K. , Jang J. , Song J. , 2023, Fundamental issues in VNAND integration toward more than 1K layers, Proc. of the 2023 IEEE International Electron Devices MeetingDOI
16 
Miyagawa H. , Kusai H. , Takaishi R. , 2019, Metal-assisted solid-phase crystallization process for vertical monocrystalline Si channel in 3D flash memory, Proc. of the 2019 IEEE International Electron Devices MeetingDOI
17 
Kim B. , Lee J. , Kang M. , 2021, The analysis of gate controllability in 3D NAND flash memory with CTF-F structure, Journal of the Institute of Electronics and Information Engineers, Vol. 25, No. 4, pp. 774-777DOI
18 
2023, Sentaurus Device User GuideGoogle Search
19 
You K. , Jin L. , Jia J. , Huo Z. , 2023, Investigation of erase cycling induced joint dummy cell disturbance in dual-deck 3D NAND flash memory, Micromachines, Vol. 14, No. 10DOI
20 
Fossum J. G. , Mertens R. P. , Lee D. S. , Nijs J. F. , 1983, Carrier recombination and lifetime in highly doped silicon, Solid-State Electronics, Vol. 26, pp. 569-576DOI
21 
Kane E. O. , 1961, Theory of tunneling, Journal of Applied Physics, Vol. 32, pp. 83-91DOI
22 
Cho W.-S. , Shim S. I. , Jang J. , 2010, Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure, Proc. of the 2010 Symposium on VLSI TechnologyDOI
23 
Malavena G. , Lacaita A. L. , Spinelli A. S. , Compagnoni C. M. , 2018, Investigation and compact modeling of the time dynamics of the GIDL-assisted increase of the string potential in 3-D NAND flash arrays, IEEE Transactions on Electron Devices, Vol. 65, pp. 2804-2811DOI
24 
Kwon D. W. , Kim W. , Kim D.-B. , 2016, Analysis on program disturbance in channel-stacked NAND flash memory with layer selection by multilevel operation, IEEE Transactions on Electron Devices, Vol. 63, pp. 1041-1046DOI
25 
Kang M. , Kim Y. , 2017, Natural local self-boosting effect in 3D NAND flash memory, IEEE Electron Device Letters, Vol. 38, pp. 1236-1239DOI
26 
Du Z. , Dong Z. , You K. , 2022, A novel program suspend scheme for improving the reliability of 3D NAND flash memory, IEEE Journal of the Electron Devices Society, Vol. 10, pp. 98-103DOI