I. INTRODUCTION

NAND flash memory has become the mainstream non-volatile storage technology owing to its high density and cost-effective scalability. In particular, the introduction of three-dimensional (3D) architectures to overcome cell-to-cell interference and area limitations has led to rapid technological advancements in 3D NAND flash memory. Recently, commercial 3D NAND products have achieved more than 300 stacked word line (WL) layers ^{[1, 2]}. Most existing 3D NAND flash memories adopt gate-induced drain leakage (GIDL)-based erase schemes. In this method, a high electric field is applied to the bit line (BL) or common source line (CSL) region during erase operation to induce GIDL current, generating holes that are injected into the channel to boost the channel potential ^{[3- 6]}. Alternatively, body erase schemes directly supply holes from a P⁺ body region to the channel, allowing for faster potential boosting. However, due to fabrication challenges in the cell-in-periphery architecture used in 3D NAND, GIDL erase has become the dominant approach ^[7]. Nevertheless, the GIDL erase mechanism suffers from a fundamental limitation: the relatively slow hole generation process leads to delayed channel potential boosting, thereby degrading erase efficiency.

Meanwhile, due to the physical limits of high aspect ratio contact etching depth, current 3D NAND processes rely on multi-deck stacking, in which the channel hole is divided into multiple decks for sequential etching and stacking ^{[8, 9]}. As the number of WL layers increases, the channel string length becomes longer, and more GIDL current is required to ensure uniform channel boosting across the full length. However, in practice, the hole injection efficiency decreases, exacerbating the speed limitations of GIDL-based erase. Consequently, a wide range of structural and electrical approaches have been investigated to improve erase performance ^{[10- 14]}. In particular, research efforts have focused on either enhancing the GIDL generation efficiency or developing alternative erase schemes that do not rely on GIDL, while ensuring that read and program operations remain unaffected ^{[15- 17]}.

Considering these limitations, we propose a novel structure called the Inter-Deck-Body (IDB) architecture, along with a corresponding fabrication methodology. In the proposed architecture, a P⁺ poly-Si IDB region is inserted between decks, and a positive voltage is applied during erase to supply holes to the channel, thereby achieving faster channel potential boosting compared to the conventional GIDL erase. The proposed structure also ensures read integrity by maintaining stable on-current during read operations. To validate the proposed IDB architecture, we performed Technology Computer-Aided Design (TCAD) simulations using Synopsys tools ^[18], verifying the functionality of read, erase, and program operations, and conducting parameter optimization for reliable performance.

II. INTER-DECK-BODY STRUCTURE

Fig. 1 illustrates the proposed Inter-Deck-Body (IDB) architecture. The IDB structure is inserted between decks of a 3D NAND flash memory array and consists of a P⁺ poly-Si IDB region and an N⁺ poly-Si channel connector. The IDB region is connected to four IDB dummy cells (IDB WL0-WL3) located above and below it. Although the IDB WLs do not function as memory cells, no actual loss in cell count occurs, as the WLs near deck interfaces in conventional multi-deck 3D NAND already serve as dummy WLs ^[19]. The P⁺ IDB region is implemented as a block-level plate structure, similar to the word lines, and is connected to a metal contact via a stair-like structure at the end of the main block, following the same contact scheme used for the word lines. While previous works have reported insertion of P⁺ poly-Si layers between decks to supply holes during erase ^[13], such approaches have a potential drawback: the P⁺ region may hinder electron channel formation during read operations, leading to a degradation in on-current. To address this issue, the proposed IDB architecture introduces an N⁺ poly-Si channel connector between the upper and lower channel regions, ensuring continuous electron conduction paths during read operation. Furthermore, the four surrounding word lines (IDB WL0-WL3) are defined as dummy word lines, distinct from main memory cells. These dummy cells are not used for data storage, but rather serve to assist erase and program operations, with electrical characteristics intentionally differentiated from the main memory array.

Fig. 1. Structure of IDB architecture in 3D NAND flash memory.

Fig. 2 illustrates the mechanisms of erase and read operations in the IDB architecture. During the erase operation, as shown in Fig. 2(a), a high positive voltage (~20 V) is applied to the P⁺ Si IDB region, while the IDB word lines (IDB WLs) are biased with a voltage below 0 V. Under these conditions, a hole inversion layer is formed at the interface region of the channel connector, enabling direct hole injection from the P⁺ Si IDB region into the channel. This hole supply facilitates channel potential boosting, which is essential for efficient erase operation. In contrast, during the read operation depicted in Fig. 2(b), the P⁺ Si IDB region is floated, and a turn-on voltage (~3 V) is applied to the adjacent IDB WLs to accumulate sufficient electrons in the channel. In this mode, the channel connector functions as an electron source for the channel and simultaneously assists in electrical continuity between decks. The channel connector serves as an electron supply path to the channel, while also assisting in the electrical connection between decks.

Fig. 2. (a) Hole injection from the IDB during the erase operation. (b) Electron channel formation during the read operation.

As the number of stacked decks continues to increase in future 3D NAND architectures, the proposed IDB structure allows additional IDBs to be inserted between each deck while maintaining a constant deck thickness. This structural feature is expected to sustain consistent erase operation speed regardless of the overall stack height. Accordingly, the proposed IDB architecture exhibits superior scalability, making it a promising candidate for future ultra-high-stack 3D NAND flash memory technologies.

Fig. 3 illustrates the fabrication flow for implementing the proposed IDB architecture. First, additional layers comprising a P⁺ poly-silicon layer, an oxide layer serving as the IDB spacer, and a hard mask layer acting as an etch stopper are deposited on top of the multiple interleaved oxide/nitride layers of the lower deck. The hard mask is used as a masking layer during the high-aspect-ratio channel hole etching process. As shown in Fig. 3(a), a channel hole etching process is then carried out to define vertical access paths. Next, as depicted in Fig. 3(b), standard 3D NAND flash memory processing is followed to form a gate stack within the channel hole, consisting of a tunneling dielectric, charge trap layer, and blocking dielectric (SiO₂/Si₃N₄/SiO₂). Subsequently, an intrinsic poly-Si channel and a filler oxide are deposited. Following this, an etch-back process is performed, as shown in Fig. 3(c), to recess the channel hole and secure the region where the channel connector will be formed. Then, as illustrated in Figs. 3(d) and 3(e), an N⁺ poly-Si channel connector is deposited, followed by a planarization step. Finally, the upper deck is constructed using the same process flow as that of the lower deck, as depicted in Fig. 3(f), completing the formation of the stacked IDB-integrated structure. The IDB structure can be fabricated with minimal additional cost, as it requires only a few supplementary deposition and etching steps beyond the conventional 3D NAND process flow.

Fig. 3. Fabrication flow of the IDB architecture.

III. OPERATION SIMULATION RESULTS

Sentaurus TCAD simulations were carried out to verify device operation and optimize key parameters, using a 3D NAND flash memory structure as shown in Fig. 4. In the simulations, mobility models accounting for doping concentration dependence and high-field saturation effects were adopted. Recombination and tunneling mechanisms were modeled using the Shockley-Read-Hall recombination model ^[20] and the nonlocal band-to-band tunneling model ^[21], respectively. The key simulation parameters used in the 3D structure are summarized in Table 1. Among these, the N⁺ poly-Si doping concentration of the channel connector ($n_{\text{Channel connector}}$) and the IDB spacer length ($L_{\text{IDB spacer}}$) were varied within the specified ranges in Table 1 for structural optimization. The doping concentration of the P⁺ IDB region ($p_{\text{IDB}}$), to which voltage is applied during operation, was set to 10²⁰ cm^-3, identical to the N⁺ doping concentration of the bit line (BL) and common source line (CSL), in order to ensure sufficient conductivity. The bias conditions applied to each electrode during read, program, and erase operations are listed in Table 2. The SSL and GSL cells, as well as the IDB WL cells, can have their threshold voltages configured through standard program and erase operations, similar to the main memory cells. In this study, the threshold voltages of the SSL and GSL cells were set to 1 V, while those of the IDB WL cells were configured to -0.5 V.

Fig. 4. TCAD simulation structure of the IDB architecture.

Unlike conventional 3D NAND flash memory, the proposed IDB architecture features a plate-type semiconductor IDB region that is connected to all channel holes within a block, thereby not electrically isolating the inter-deck regions between adjacent channel hole strings. As a result, there is a potential risk of read current leakage between adjacent channel holes through the P⁺ IDB region. Key parameters influencing this undesired leakage include the voltages applied to IDB WL0 and IDB WL1 during read operation (V_{IDB WL0}, V_{IDB WL1}) and the IDB spacer length ($L_{\text{IDB spacer}}$). To investigate design conditions that effectively suppress this leakage, simulations were performed as illustrated in Fig. 5. Fig. 5(a) shows the simulated structure, which consists of two adjacent channel holes (strings). The cross-sectional view of the structure is shown in Fig. 5(b), where different voltages were applied to the two strings to create two distinct conditions: current flow through an on-cell in the BL0 string, and no current flow due to an off-cell in the BL1 string. The occurrence of read current leakage between strings was analyzed based on the electron density distribution within the P⁺ IDB region during read operation, as shown in Fig. 5(c).

Fig. 5. (a) 3D TCAD simulation structure to evaluate read current leakage through the IDB electrode. (b) Cross sectional view of the simulation structure including read target string (BL 0) and the read inhibit string (BL 1). (c) Electron density distribution in the IDB electrode between BL 0 and BL 1.

A total of three structural and operational parameters were evaluated to investigate their impact on read current leakage. The simulated conditions include: (1) the voltage applied to IDB WL1 and WL2 adjacent to the P⁺ Si IDB region (V_{IDB WL0}, V_{IDB WL1} = 3 V or 6 V), (2) the IDB spacer length ($L_{\text{IDB spacer}}$ = 20 nm or 40 nm), and (3) the doping concentration of the channel connector ($n_{\text{Channel connector}}$ = 10¹⁹ cm^-3 or 10²⁰ cm^-3). The simulation results are summarized in Fig. 6. Among the parameters, $n_{\text{Channel connector}}$ was found to have a minimal impact on the electron density in the P⁺ Si IDB region. In contrast, increasing $L_{\text{IDB spacer}}$ and reducing V_{IDB WL0} and V_{IDB WL1} significantly reduced the electron concentration within the IDB region. Specifically, when $L_{\text{IDB spacer}}$ = 40 nm and V_{IDB WL0} = V_{IDB WL1} = 3 V, the electron density in the IDB region was reduced to approximately 10¹⁰ cm^-3, which is close to the intrinsic silicon level. These results suggest that applying a voltage of 3 V or lower to IDB WL1 and WL2, combined with an IDB spacer length of at least 40 nm, can effectively suppress undesired read current leakage through the IDB region during read operation.

Fig. 6. Electron density distribution in the IDB region during the read operation with varying LIDB spacer and nChannel connector. The electron density distribution was extracted after the applied voltage had completely risen. (a) Electron density distribution under VIDB WL 1, 2 = 3 V. (b) Electron density distribution under at VIDB WL 1, 2 = 6 V.

Subsequently, the effect of $n_{\text{Channel connector}}$ and $L_{\text{IDB spacer}}$ on the on-current during read operation was analyzed, as shown in Fig. 7, and compared with that of conventional 3D NAND flash memory. First, the on-current characteristics with varying $L_{\text{IDB spacer}}$ were evaluated with $n_{\text{Channel connector}}$ = 10¹⁹ cm^-3 fixed, as shown in Fig. 7(a). The results indicate that the on-current increases as the $L_{\text{IDB spacer}}$ decreases. This trend is attributed to the stronger fringing field from the IDB WL, which induces more electrons in the channel when the spacer length is shorter. Next, Fig. 7(b) presents the on-current variation with respect to $n_{\text{Channel connector}}$, where $L_{\text{IDB spacer}}$ is fixed at 40 nm. The simulation results show that increasing $n_{\text{Channel connector}}$ leads to higher on-current. This is likely due to enhanced electrical coupling between adjacent decks via the channel connector as its doping concentration increases. Based on the simulation results in Fig. 7, it can be concluded that maintaining $L_{\text{IDB spacer}}$ $\le$ 40 nm and $n_{\text{Channel connector}}$ $\ge$ 10¹⁹ cm^-3 allows the proposed IDB structure to achieve an on-current level comparable to that of conventional 3D NAND flash memory.

Fig. 7. (a) On-current characteristics and electron density during the read operation depending on LIDB spacer. (b) On-current characteristics and electron density during the read operation depending on nChannel connector. The number of WLs are fixed at 100, and all other structural parameters unspecified were kept identical.

As shown in Fig. 8, the channel potential boosting speed during the erase operation was analyzed as a function of the n-channel connector doping concentration ($n_{\text{Channel connector}}$) and compared with that of a conventional 3D NAND flash memory. In the IDB architecture, the $L_{\text{IDB spacer}}$ was fixed at 40 nm to suppress read current leakage through the IDB region while maintaining sufficient on-current during read operation. Under this condition, the variation in channel potential boosting speed was evaluated with respect to the $n_{\text{Channel connector}}$.

Fig. 8. (a) Erase pulse schemes for the IDB 3D NAND and conventional 3D NAND architectures. (b) Channel potential boosting depending on the n-channel connector. The LIDB spacer is set to 40 nm in all cases.

In the conventional 3D NAND structure, hole injection was achieved by inducing GIDL at both the bit-line and common-source-line ends. In contrast, the IDB architecture utilized a P⁺ IDB region for hole injection. To ensure a fair comparison, the channel potential was monitored at the location farthest from the hole injection point. The number of word lines in each string was set to 100 for both structures. The applied erase voltage waveforms are depicted in Fig. 8(a). As shown in the simulation results of Fig. 8(b), when the doping concentration of the n-channel connector exceeded 5 $\times$ 10¹⁹ cm^-3 in the IDB architecture, the channel potential boosting speed during erase degraded significantly. These results indicate that, in order to achieve faster boosting compared to the conventional structure, the doping concentration of the n-channel connector should be maintained below 1 $\times$ 10¹⁹ cm^-3.

Table 3 summarizes the final set of optimized parameters that satisfy all key design requirements, including suppression of read current leakage through the IDB region during read operation, maintenance of on-current comparable to that of conventional 3D NAND flash memory, and enhancement of channel potential boosting speed during erase. Based on the data in Table 3, it was confirmed that setting the IDB spacer length to 40 nm and the n-channel connector doping concentration to 1 $\times$ 10¹⁹ cm^-3 meets all of the aforementioned operational criteria.

Fig. 9 presents simulation results comparing the erase performance of the proposed IDB architecture with that of conventional 3D NAND flash memory, based on the optimized parameter set. During the erase operation, the channel potential was extracted at the center of the string to evaluate the boosting speed. Fig. 9(a) shows the comparison of channel potential boosting speed between the IDB architecture and the conventional 3D NAND flash memory under varying V_GIDL conditions. The number of word lines was set to 100. As previously reported ^[23], the boosting speed in conventional 3D NAND increases with higher V_GIDL (= V_BL(CSL) - V_SSL(GSL)); however, even at V_GIDL = 15 V, it remained lower than that of the IDB architecture. Furthermore, it was observed that the peak channel potential at the end of the boosting phase in the IDB architecture was 0.5-2.5 V higher than that of the conventional structure. This result confirms that the IDB architecture provides improved erase efficiency under the same applied voltage conditions. Fig. 9(b) compares the boosting speed as a function of $N_{\text{WL}}$ for both the IDB and conventional structures. While the conventional 3D NAND exhibited a significant degradation in channel potential boosting speed with increasing $N_{\text{WL}}$, the IDB architecture maintained consistent boosting performance regardless of string length. In the case of GIDL-based erase, the supply of holes is limited due to the band-to-band tunneling mechanism, and a larger number of holes is required to maintain the same channel potential as $N_{\text{WL}}$ increases, leading to slower boosting. In contrast, in the IDB architecture, holes are majority carriers in the P⁺ Si region and can be directly supplied to the channel through drift without additional generation processes. As a result, the boosting speed remains unaffected by $N_{\text{WL}}$. These results suggest that the IDB architecture can achieve more efficient erase operations than conventional GIDL-based 3D NAND flash memory, particularly in long strings with a large number of stacked word lines.

Fig. 9. (a) Comparison of channel potential boosting speed between the IDB architecture and conventional 3D NAND, depending on VGIDL during the erase operation. (b) Comparison of channel potential boosting speed between the IDB architecture and conventional 3D NAND, depending on the NWL during the erase operation.

The program operation was finally verified, as illustrated in Fig. 10. During programming, the voltage applied to the IDB WL (V_{IDB WL_PGM}) must be higher than the threshold voltage of the IDB WL dummy cell (V_{th_IDB WL}) to ensure vertical channel connection between the upper and lower decks in the selected string. In contrast, for unselected strings, the condition V_{IDB WL_PGM} - V_{th_IDB WL} $\le$ V_{SSL_PGM} - V_{th_SSL} must be satisfied so that the IDB WL transistor can be reliably turned off through bit-line precharge operation, similar to the SSL transistor. In this simulation, V_{IDB WL_PGM} was set to 0 V. As a result, the channel potential in the selected string was successfully maintained at 0 V, while the channel in the unselected string was self-boosted, confirming that program inhibition was effectively achieved.

Fig. 10. (a) Cross-sectional simulation results of the selected and unselected strings during program operation. (b) Channel potential profiles of the selected and unselected strings.

IV. CONCLUSION

This work proposed an Inter-Deck-Body (IDB) architecture to enhance the erase performance of 3D NAND flash memory. By introducing a P⁺ IDB region between decks, the proposed structure enables direct hole injection into the channel without relying on GIDL, thereby accelerating the channel potential boosting during erase. The proposed scheme also maintains read integrity by suppressing current leakage through optimized IDB WL biasing and spacer design, and it ensures effective program inhibition via self-boosting in unselected strings. Furthermore, the erase performance remained stable even with increasing string length, highlighting the scalability of the architecture for ultra-high-stack implementations. Overall, the IDB architecture provides a promising solution for future 3D NAND flash technologies, offering improved erase speed and robust read/program reliability.