Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2026-04 (Vol.26 No.02)
  4. 10.5573/JSTS.2026.26.2.150
XML PDF INFO REF

REFERENCES

1 
Okhonin S. , Nagoga M. , Sallese J.-M. , Fazan P. , 2001, A capacitor-less SOI 1T DRAM concept, Proc. of IEEE International SOI Conference, pp. 153-154DOI
2 
Ohsawa T. , Fujita K. , Higashi T. , Iwata Y. , Kajiyama T. , Asao Y. , Sunouchi K. , 2002, Memory design using a one-transistor gain cell on SOI, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1510-1521DOI
3 
Kuo C. , King T.-J. , Hu C. , 2002, A capacitorless double-gate DRAM cell design for high-density applications, IEDM Technical Digest, pp. 843-846DOI
4 
Okhonin S. , Nagoga M. , Sallese J.-M. , Fazan P. , 2002, A capacitor-less 1T-DRAM cell, IEEE Electron Device Letters, Vol. 23, No. 2, pp. 85-87DOI
5 
Kuo C. , King T.-J. , Hu C. , 2003, A capacitorless double-gate DRAM technology for sub-100-nm embedded and stand-alone memory applications, IEEE Transactions on Electron Devices, Vol. 50, No. 11, pp. 2408-2416DOI
6 
Seo J. H. , Yoon Y. J. , Yu E. , Sun W. , Shin H. , Kang I. M. , Lee J.-H. , Cho S. , 2019, Fabrication and characterization of a thin-body poly-Si 1T DRAM with charge-trap effect, IEEE Electron Device Letters, Vol. 40, No. 3, pp. 431-434DOI
7 
Ansari M. H. R. , Navlakha N. , Lee J. Y. , Cho S. , 2020, Double-gate junctionless 1T DRAM with physical barriers for retention improvement, IEEE Transactions on Electron Devices, Vol. 67, No. 4, pp. 1471-1479DOI
8 
Ansari M. H. R. , Cho S. , 2021, Performance improvement of 1T DRAM by raised source and drain engineering, IEEE Transactions on Electron Devices, Vol. 68, No. 4, pp. 1577-1583DOI
9 
Yoon Y. J. , Seo J. H. , Cho S. , Lee J.-H. , Kang I. M. , 2019, A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance, Applied Physics Letters, Vol. 114, No. 18, pp. 183503-1-183503-4DOI
10 
Lin J.-T. , Lin H.-H. , Chen Y.-J. , Yu C.-Y. , Kranti A. , Lin C.-C. , Lee W.-H. , 2017, Vertical transistor with n-bridge and body-on-gate for low-power 1T-DRAM application, IEEE Transactions on Electron Devices, Vol. 64, No. 12, pp. 4937-4945DOI
11 
Kim S. , Lee S.-Y. , Park S. , Kim K. R. , Kang S. , 2020, A logic synthesis methodology for low-power ternary logic circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 12, pp. 4749-4759DOI
12 
Zahoor F. , Zulkifli T. Z. A. , Khanday F. A. , Murad S. A. Z. , 2020, Carbon nanotube and resistive random access memory based unbalanced ternary logic gates and basic arithmetic circuits, IEEE Access, Vol. 8, pp. 104701-104716DOI
13 
Sandhie Z. T. , Ahmed F. U. , Chowdhury M. H. , 2022, Design of novel 3T ternary DRAM with single word-line using CNTFET, Microelectronics Journal, Vol. 126, pp. 105498-1-105498-6DOI
14 
Bishop M. D. , Hills G. , Srimani T. , Lau C. , Murphy D. , Fuller S. , Humes J. , Ratkovich A. , Nelson M. , Shulaker M. M. , 2020, Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities, Nature Electronics, Vol. 3, No. 9, pp. 492-501DOI
15 
Yin Z. , Ding A. , Zhang H. , Zhang W. , 2022, The relevant approaches for aligning carbon nanotubes, Micromachines, Vol. 13, No. 12, pp. 1863-1-1863-12DOI
16 
Lin Y.-M. , Appenzeller J. , Knoch J. , Avouris P. , 2005, High-performance carbon nanotube field-effect transistor with tunable polarities, IEEE Transactions on Nanotechnology, Vol. 4, No. 5, pp. 481-489DOI
17 
Prakash P. , Sundaram K. M. , Bennet M. A. , 2018, A review on carbon nanotube field-effect transistors (CNTFETs) for ultra-low power applications, Renewable and Sustainable Energy Reviews, Vol. 89, pp. 194-203DOI
18 
Gupta A. , Saurabh S. , 2021, Implementing a ternary inverter using dual-pocket tunnel field-effect transistors, IEEE Transactions on Electron Devices, Vol. 68, No. 11, pp. 5305-5310DOI
19 
Kamal N. , Kamal A. K. , Singh J. , 2021, L-shaped tunnel field-effect transistor-based 1T DRAM with improved read current ratio, retention time, and sense margin, IEEE Transactions on Electron Devices, Vol. 68, No. 6, pp. 2705-2711DOI
20 
Kim M. , Ha J. , Kwon I. , Han J.-H. , Cho S. , Cho I. H. , 2018, A novel one-transistor dynamic random-access memory (1T DRAM) featuring partially inserted wide-bandgap double barriers for high-temperature applications, Micromachines, Vol. 9, No. 11, pp. 581-1-581-9DOI
21 
Navlakha N. , Lin J.-T. , Kranti A. , 2016, Improved retention time in twin-gate 1T DRAM with tunneling-based read mechanism, IEEE Electron Device Letters, Vol. 37, No. 8, pp. 1127-1130DOI
22 
Schenk A. , 1993, Rigorous theory and simplified model of the band-to-band tunneling in silicon, Solid-State Electronics, Vol. 36, No. 1, pp. 19-34DOI
23 
Shockley W. , Read W. T. , 1952, Statistics of the recombinations of holes and electrons, Physical Review, Vol. 87, pp. 835-842DOI
24 
Hall R. N. , 1952, Electron-hole recombination in germanium, Physical Review, Vol. 87, pp. 387DOI