I. INTRODUCTION

In modern data-centric computing environments, achievement of high performance and high integration in memory devices has become a critical challenge. The conventional one-transistor–one-capacitor dynamic random-access memory (1T1C DRAM) structure offers high data storage density; however, as device dimensions continue to scale down, it becomes increasingly difficult to miniaturize both the transistor and the capacitor. To address this issue, capacitor-less one-transistor dynamic random access memory (1T DRAM), which allows data storage without the need for a separate capacitor, has attracted considerable attention ^{[1- 10]}. This technology is regarded as a promising alternative due to its structural simplicity and excellent compatibility with complementary metal-oxide–semiconductor (CMOS) fabrication processes, enabling both high performance and compact integration. Furthermore, capacitor-less 1T DRAM simplifies circuit design and enhances integration density. Therefore, it addresses the limitations of conventional DRAM architectures and contributes to the development of efficient, high-density memory solutions.

Meanwhile, conventional DRAMs face inherent limitations in terms of data storage capacity and power efficiency. To overcome these challenges, ternary logic–based memory systems have emerged as a promising alternative ^[11]. Ternary logic allows each memory cell to represent three distinct states (0, 1, and 2), thereby increasing data storage density by approximately 1.5 times. It also offers advantages such as reduced circuit complexity and lower power consumption ^[12]. These characteristics are particularly beneficial in nanoscale computing environments, where data transfer demands are rapidly increasing and energy efficiency is of growing importance. By integrating the structural simplicity of 1T DRAM with the storage efficiency of ternary logic, it is possible to realize next-generation memory technologies that offer significantly enhanced storage density, improved power efficiency, and simplified circuit design.

Recently, ternary logic implementations using carbon-nanotube field effect transistors (CNTFETs) have been actively studied. However, their practical application remains limited due to manufacturing complexity and challenges in mass production ^[13]. In particular, CNTFETs exhibit limited compatibility with conventional silicon-based CMOS processes, posing significant challenges for rapid adoption within the semiconductor industry. Especially, CNTFET-based devices require additional alignment and chirality-selection steps, which not only elevate fabrication costs but also increase overall process complexity ^[14]. While CNTFETs offer the advantage of enabling ternary logic by adjusting the threshold voltage, they face issues such as difficulty in maintaining uniform nanotube alignment and the presence of metallic CNTs, which lead to leakage-current problems ^{[15- 17]}. To overcome these limitations, research efforts are increasingly focused on implementing ternary logic using conventional transistor-based approaches ^[18].

In this study, we propose a novel ternary 1T DRAM device that combines the structural advantages of silicon-based capacitor-less 1T DRAM with the efficiency of a ternary logic system. Silicon-based devices offer significant advantages in terms of manufacturability and reliability, as they are fully compatible with conventional semiconductor fabrication processes. Benefiting from decades of process optimization, silicon devices exhibit stable manufacturing characteristics and high uniformity, making them well-suited for mass production. In particular, the implementation of ternary logic using silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI MOSFETs) presents a promising alternative, as it is compatible with existing CMOS processes and can be adopted without the need for additional process development. This study presents the feasibility and electrical characteristics of the proposed device through technology computer-aided design (TCAD) simulations and suggests optimization strategies to enhance its performance.

II. DEVICE STRUCTURE

Figs. 1(a) and 1(b) show the structure of the proposed device. The proposed device is essentially fabricated on a silicon on insulator wafer containing buried oxide. The device adopts a p$^+$-i-n$^+$ configuration, featuring an intrinsic channel region between a p$^+$ source and an n$^+$ drain. The source and drain doping concentrations are both 1$\times$10$^{20}$ cm$^{-3}$, while the channel doping concentration is 5 $\times$ 10$^{15}$ cm$^{-3}$, respectively. Although the structure is similar to that of a tunneling field-effect transistor (TFET), it incorporates a 100 nm-long lightly doped drain (LDD) region doped at 1 $\times$ 10$^{18}$ cm$^{-3}$ to alleviate electric-field concentration between the gate, source, and drain, thereby enabling controlled tunneling behavior. In addition, two quantum wells (QWs) with widths of 60 nm and 80 nm, respectively, are formed within a 200 nm-thick body region through p-type doping of 5 $\times$ 10$^{18}$ cm$^{-3}$. These QWs distinguish three states (0, 1, and 2) by the amount of stored charge during the write operation, which subsequently modulates the drain current. The electrical characteristics of the proposed 1T DRAM device were analyzed using two-dimensional (2D) device simulations performed with the Sentaurus TCAD simulator. To ensure the accuracy and reliability of the simulation results, various physical models were employed, including doping-dependent mobility, bandgap narrowing, band-to-band tunneling (BTBT), and Auger and Shockley–Read–Hall (SRH) recombination mechanisms. A detailed summary of the mobility, recombination, and tunneling models used in the simulations is provided in Table 1.

Fig. 1. (a) Structure of the proposed device (b) dimensions of double quantum well in the proposed device.

III. RESULT AND DISCUSSION

In proposed device, the stored state is read by transferring electrons stored in the quantum wells to the drain and distinguishing among three different states based on the resulting current level, which depends on the differentiated amount of electrons stored in the double QWs. As illustrated in Fig. 2, the number of electrons stored in the quantum wells is controlled by applying specific voltages to the gate and drain during the write operation. Depending on the target state, the gate voltage is set to 1.5 V for writing ‘2’ and 0.8 V for writing ‘1’. This scheme is designed such that a higher positive voltage is applied for state ‘2’ than for state ‘1’, allowing the storage of a greater number of electrons.

Fig. 2. Device operation and bias configuration. (a) Write ‘0’. (b) Write ‘1’. (c) Write ‘2’.

Furthermore, the write ‘0’ operation is implemented by applying a negative voltage ($-1.0$ V) to the gate and a positive voltage (1.0 V) to the drain, facilitating the removal of electrons stored in the quantum wells by transferring them from the wells to the drain.

Fig. 3 shows the electron density distributions inside the device after different write states. In the write ‘2’ state, a very high electron density is observed in both quantum wells, where the peak electron density in well 1 reaches approximately 8$\times$10$^{15}$ cm$^{-3}$. In contrast, for the write ‘1’ state, electron accumulation mainly occurs in well 2, while the electron density in well 1 is significantly reduced to about 9 $\times$ 10$^{11}$ cm$^{-3}$. For the write ‘0’ state, the electron density in both quantum wells remains very low, on the order of 1$\times$10$^8$ cm$^{-3}$. These results confirm that electron storage within the quantum wells varies according to the specific write operation.

Fig. 3. Distribution of stored electrons in QWs after write process.

During the hold operation, appropriate gate, source, and drain biases are applied to maintain charge confinement in the quantum wells and suppress unintended carrier transport. A moderate positive gate bias is applied to preserve the potential well structure, enabling the stored electrons to remain confined during the hold period. A negative source bias (Vs = $-0.5$ V) increases the potential barrier between the source and well 1, thereby suppressing thermally activated electron leakage toward the p$^+$ source region. Meanwhile, a small positive drain bias (Vd = 0.2 V) is applied to relax the electric field near the drain–well junction and inhibit unintended electron injection from the n$^+$ drain into well 2. Through this combined biasing scheme, both outward leakage and inward carrier injection are effectively suppressed, resulting in improved charge retention stability. Fig. 4 shows the bias scheme and operation principles.

Fig. 4. Operational diagram for hold state.

In addition, a positive voltage of 0.5 V is applied to the gate to suppress the diffusion of stored electrons within the QWs, thereby stably maintaining the stored state.

The read operation is performed by applying $-0.3$ V to the gate and 0.1 V to the drain, allowing the stored electrons in the QWs to transfer to the drain and thereby enabling state detection. Fig. 5 illustrates the changes in drain current and the peak electron density in the QWs when the read voltage is applied for 30 ns following the write ‘2’ operation. Simulation results show that as the drain current decreases during the read operation, the peak electron density in the quantum wells also decreases. This observation indirectly confirms that the electrons stored in the quantum wells contribute to current formation by moving toward the drain. These findings validate the effectiveness of the proposed device’s volatile read mechanism, which resembles that of a 1T1C DRAM architecture.

Fig. 5. Transient characteristics of the drain current and peak electron density in well ‘2’ during the read operation.

The transient simulation was performed for 90 ns, and the drain current and current ratio for each state were analyzed based on the information stored during the write operation. As shown in Fig. 6, the drain currents for the read ‘2’, read ‘1’, and read ‘0’ states were found to be 5$\times$10$^{-8}$, 8.5$\times$10$^{-11}$, and 3.5$\times$10$^{-14}$ A/µm, respectively. The current ratios between the states were confirmed to be I$_2$/I$_1$ = 5.9$\times$10$^2$ and I$_1$/I$_0$ = 2.4$\times$10$^3$. Notably, the current ratio between state ‘2’ and state ‘0’ reached 1.4$\times$10$^6$, demonstrating the excellent switching characteristics of the proposed structure ^{[19, 20]}.

Fig. 6. Drain current characteristics with various operation states at 300 K.

Figs. 7(a) and 7(b) present the changes in electrical characteristics when a read operation is performed after maintaining the hold state. During this period, both the electron concentration in well 2 and the drain current in the ‘2’ state decrease as the hold time increases. Eventually, the drain current of the ‘2’ state converges to the initial drain current of the ‘1’ state, measured at 8.5$\times$10$^{-11}$ A/µm. Beyond this point, the distinction between the ‘2’ and ‘1’ states becomes increasingly ambiguous. As shown in Fig. 7(b), after approximately 120 ms, the charge stored in the quantum wells equalizes, rendering the two states indistinguishable.

Fig. 7. Hole time dependent characteristics of (a) drain current (b) electron concentration.

To evaluate the applicability of the proposed device in high-temperature environments, the operating temperature was increased and the device characteristics were measured. Fig. 8 shows the variation in drain current under two temperature conditions, 300 K and 373 K. As the temperature increases, thermionic emission and SRH recombination are activated, which imposes limitations on the stable maintenance of conventional DRAM operation in the proposed device.

Fig. 8. Transient drain current characteristics at 300 K and 373 K.

In particular, at elevated temperatures, enhanced thermal activation causes thermionic emission to become the dominant mechanism, allowing electrons stored in the quantum wells to more readily overcome the potential barriers and thereby significantly increasing carrier transport. As a result, the drain current increases for both state ‘1’ and state ‘0’, leading to a reduction in the current ratio between the states and making state discrimination more difficult. Notably, at 373 K, the current difference between state ‘2’ and state ‘1’ is significantly reduced, indicating a degraded sensing margin. This behavior originates from the strengthened thermionic emission under high-temperature conditions, which increases electron injection and residual charge during the write operation, and is consistent with previously reported results on high-temperature 1T DRAM operation ^{[20, 21]}.

On the other hand, band-to-band tunneling (BTBT) is primarily governed by the electric field and exhibits relatively weak temperature dependence; therefore, it does not act as the dominant mechanism responsible for the high-temperature characteristics observed in this study ^[22].

Meanwhile, SRH recombination is further enhanced at elevated temperatures due to increased trap occupancy and carrier generation rates, thereby accelerating charge loss during the hold operation and contributing to the degradation of retention characteristics ^{[23, 24]}. The combined effects of these leakage mechanisms increase the drain current of both state ‘1’ and state ‘0’ after the write operation, resulting in a reduced current ratio and sensing margin. Consequently, the retention time is also expected to be significantly reduced under high-temperature operating conditions.

To alleviate this issue, the doping concentration of the barrier region was increased from the original 5 $\times$ 10$^{18}$ cm$^{-3}$ to 1$\times$10$^{20}$ cm$^{-3}$, and the results were shown in Fig. 9(a). According to the result, the I$_2$/I$_1$ current ratio was found to be most optimal when the doping concentration of the barrier region was 1 $\times$ 10$^{20}$ cm$^{-3}$. This is because, as the doping concentration increases, the electron concentration stored in the well during the write operation for State 1 decreases, leading to a significant increase in the I$_2$/I$_1$ ratio. In particular, the most effective result was observed when the doping concentration was 1$\times$10$^{20}$ cm$^{-3}$. At 373 K, as shown in Fig. 9(b), the barrier doping concentration must be adjusted to 1$\times$10$^{20}$ cm$^{-3}$ to achieve a valid I$_2$/I$_1$ current ratio.

Fig. 9. (a) Impact of barrier doping on electron concentration and I$_2$/I$_1$ at well2 after write ‘1’, (b) energy band comparison between original and optimized device.

Increasing the barrier doping concentration to 1$\times$10$^{20}$ cm$^{-3}$ effectively improves the I$_2$/I$_1$ current ratio. However, several potential trade-offs should also be considered. A highly doped barrier region may result in increased junction abruptness at the interface between the barrier and the adjacent channel region, which can enhance local electric fields and potentially affect long-term device reliability. In addition, excessively high doping concentrations may increase ionized impurity scattering, leading to degraded carrier mobility and a possible increase in series resistance.

From a fabrication perspective, realizing such a high doping concentration with an abrupt profile may introduce additional challenges in process control, including dopant activation efficiency and suppression of diffusion-induced profile broadening.

At 373 K, the drain currents for the read ‘2’, read ‘1’, and read ‘0’ states were measured as 3.9 $\times$ 10$^{-8}$, 1.7$\times$10$^{-10}$, and 1.0$\times$10$^{-14}$ A/µm, respectively. The current ratios between the states were found to be I$_2$/I$_1$ = 1.1 $\times$ 10$^3$ and I$_1$/I$_0$ = 3.5 $\times$ 10$^3$, indicating that a current ratio greater than 10$^3$ can be achieved between each state. A comparison of the operation at 373 K between the existing and improved structures reveals a clear distinction between state ‘2’ and state ‘1’ in the improved structure, effectively resolving the minor current ratio issue observed in the existing structure, as shown in Fig. 10. This result demonstrates that even in high-temperature environments, the proposed structure can provide reliable memory operation through an increased doping concentration in the barrier region and control of the hold voltage.

Fig. 10. Transient simulation comparison between original and optimized device at 373 K.

Figs. 11(a) and 11(b) show the results of the read operation performed after maintaining the hold state for a certain duration. During this period, the electron concentration in well 2 and the drain current in state ‘0’ increased as the hold time increased, eventually reaching a point where it matched the initial drain current of state ‘1’, which was 1.7 $\times$ 10$^{-10}$ A/µm. Beyond this point, the difference between state ‘0’ and state ‘1’ gradually becomes indistinguishable, and after approximately 11 ms, it becomes impossible to distinguish between the two states.

Fig. 11. Hold time characteristics with optimized structure at 373 K (a) drain current and (b) electron concentration.

IV. CONCLUSIONS

In this study, a ternary-based 1T DRAM device utilizing a quantum well was proposed, and its electrical characteristics were analyzed through TCAD Sentaurus simulations. The proposed device combines the structural advantages of the existing capacitor-less 1T DRAM with the high data-storage efficiency of ternary logic, offering the potential for increased data-storage density and reduced power consumption. Simulation results of the write, read, and hold operations confirmed that the proposed device can clearly distinguish among three states (0, 1, and 2) by controlling the number of electrons stored in the quantum wells.

In addition, by optimizing the doping concentration in the barrier region and adjusting the gate hold voltage, the proposed device is shown to maintain excellent current ratios and stable retention characteristics even under high-temperature operation at 373 K.

While previously reported CNTFET-based ternary logic or memory devices often suffer from process complexity and limitations in large-scale manufacturability, the proposed silicon-based ternary 1T DRAM provides a practical and process-friendly alternative.

Table 2 presents a qualitative comparison between CNTFET-based ternary DRAMs, TFET-based ternary logic/memory structures, and the proposed device in terms of device platform, ternary-state control mechanism, scalability, and CMOS compatibility.

Through this comparison, it is demonstrated that the proposed device effectively enhances the practical feasibility of ternary memory implementation while preserving high compatibility with conventional CMOS processes, thereby offering a promising solution for future multi-valued memory applications.