| Title |
Investigation of Ternary Operation 1T DRAM with Double Quantum Well Structure |
| Authors |
(Min-Ju Lee) ; (Seong-Ho Kim) ; (Ga-Hyun Shin) ; (Jae-Sung Park) ; (Woo Young Choi) ; (Il Hwan Cho) |
| DOI |
https://doi.org/10.5573/JSTS.2026.26.2.150 |
| Keywords |
Ternary logic; 1T DRAM; quantum well; reliability |
| Abstract |
In the pursuit of high-performance and high-density memory solutions for modern data-centric applications, capacitor-less one-transistor dynamic random-access memory (1T DRAM) has emerged as a promising alternative to conventional one transistor one capacitor dynamic random access memory (1T1C DRAM) structures. This study proposes a silicon-based ternary 1T DRAM device that integrates the structural simplicity of capacitor-less 1T DRAM with the enhanced data-storage efficiency of ternary logic, enabling each cell to represent three distinct states (0, 1, and 2). Different from the carbon-nanotube-FET (CNTFET)-based ternary devices, which face significant challenges in manufacturability and process integration, the proposed device leverages standard silicon-on-insulator (SOI) MOSFET technology, ensuring compatibility with existing complementary metaloxide-semiconductor (CMOS) fabrication processes. Through TCAD Sentaurus simulations, we demonstrate the feasibility of the proposed architecture, validating clear state separation during write, read, and hold operations by controlling the number of electrons stored in quantum wells. Furthermore, the device exhibits excellent thermal stability up to 373 K, maintaining robust current ratios and retention characteristics. This work provides a practical and scalable pathway toward ternary-memory implementation, contributing to the development of next-generation memory systems with improved integration density and energy efficiency. |