Performance and Reliability Improvement of Double-gate Structure-based Flexible PBTTT
Organic Thin-film Transistors
Ah-Hyun Hong1,2,†
Hyungjun Choi1,2,†
Kyeungbin Kim1,2
Dong-Wook Park1,2,*
-
(School of Electrical and Computer Engineering, University of Seoul, Seoul, 02504,
South Korea)
-
(Center for Semiconductor Research, University of Seoul, Seoul, 02504, South Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Organic thin-film transistor (OTFT), Parylene-C, PBTTT, Flexible OTFT, Double-gate structure
I. INTRODUCTION
Significant research efforts have been devoted to the development of thin-film transistor
(TFT) technologies for integration into flexible displays and wearable electronic
systems [1,
2]. Among various TFT platforms, organic thin-film transistors (OTFTs) have attracted
considerable attention due to their mechanical flexibility and solution processability,
enabling low-cost and high-throughput manufacturing [3-
5]. In addition, OTFTs are well-suited for flexible device fabrication because their
electrical characteristics are less constrained by the substrate compared with those
of many conventional electronic devices [6-
11]. Owing to these advantages, OTFTs have been extensively investigated and increasingly
adopted in flexible electronics, including flexible sensors and wearable devices.
Furthermore, their high chemical and physical responsiveness enable their use as transducers
for a wide range of sensing modalities, such as pH, humidity, glucose, and light [12-
15]. When biocompatible organic materials are employed, OTFTs can further function as
biosensors. As their application scope continues to expand, significant efforts have
been devoted to improving device reliability and operational stability [16].
Nevertheless, conventional single-gate (SG) OTFTs still face inherent limitations,
including relatively low carrier mobility compared with inorganic TFTs and vulnerability
to ambient species such as oxygen and moisture [17-
20]. To address these issues, extensive studies have been conducted on encapsulation
strategies, along with parallel investigations into gate-insulator materials and processes
that critically influence transistor performance. Furthermore, continued device scaling
and the associated reduction in channel length have increased the need for structural
innovations to maintain performance and stability.
As a structural approach to overcome these limitations, we adopted a double-gate (DG)
structure in poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT)-based
OTFTs. Because the channel is modulated by two gates, DG devices can offer enhanced
stability and improved electrical performance relative to SG counterparts, making
them attractive for analog-circuit applications [21]. PBTTT exhibits high charge-carrier mobility due to its highly ordered lamellar packing
and strong π–π stacking, enabling efficient charge transport in OTFTs. In addition,
its solution processability and mechanical flexibility make it suitable for low-temperature
fabrication of large-area and flexible electronic devices. The fabricated PBTTT OTFTs
employed Parylene-C as both the flexible substrate and the gate dielectric. Their
reliability and stability were evaluated under mechanical stress in a typical ambient
environment [22,
23]. The results were obtained from representative SG and DG devices based on multiple
device measurements (n > 5) and were systematically compared to analyze changes in
device performance and reliability.
II. PROPOSED DOUBLE GATE OTFT
1. Structure of Double-gate PBTTT OTFT
Fig. 1(a) illustrates the device structure of the DG OTFT. The device was fabricated by forming
a top-gate insulator (TGI) and a top gate on a coplanar bottom-gate structure, and
separate contact pads were implemented to apply bias voltages to each gate independently.
Fig. 1(b) presents a cross-sectional view of the DG OTFT obtained by focused ion beam (FIB)
analysis. Fig. 1(c) shows the architecture of the SG OTFT fabricated in a coplanar bottom-gate configuration,
and Fig. 1(d) provides the corresponding FIB cross-sectional image. Fig. 1(e) summarizes the fabrication process flow for the DG OTFT.
Fig. 1. Device concept and physical characterization of the PBTTT OTFT. (a) 2D schematic
image of the double-gate (DG) PBTTT OTFT, (b) FIB cross-sectional image of the DG
OTFT, (c) 2D schematic image of single-gate (SG) PBTTT OTFT, (d) FIB cross-sectional
image of the SG OTFT, and (e) fabrication process of DG OTFT devices.
III. MEASUREMENT RESULTS
1. Single-gate PBTTT TFT Characteristics and Long-term Reliability
To evaluate device stability under stress, the transfer and output characteristics
of the SG PBTTT OTFTs were measured and used as a reference for comparison. Figs. 2(a) and 2(b) show the transfer and output curves measured under the flat condition, confirming
that the fabricated SG OTFT operated with an on/off ratio of approximately 105.
In addition, long-term stability was evaluated by monitoring the devices for 40 days
under identical ambient conditions, with and without SU-8 passivation. Fig. 2(c) and 2(d) show the temporal change in subthreshold swing (SS) and field-effect mobility over
the 40 days, respectively.
Fig. 2. Electrical characteristics of the single-gate (SG) PBTTT OTFT. (a) Transfer
curves and (b) output curves of the SG OTFT measured under the flat condition. (c)
Time-dependent trends in subthreshold swing and (d) field-effect mobility of the SG
OTFT with and without SU-8 passivation.
For devices without SU-8 passivation, a rapid degradation in SS and mobility was observed,
and the devices failed to operate after approximately 10 days. In contrast, passivated
devices maintained their performance throughout the 40-day test. Based on these results,
an SU-8 passivation layer was employed for subsequent experiments to ensure long-term
operation.
2. Durability After Negative Gate-bias Stress (NGBS) and Bending Stress
To analyze device performance changes induced by NGBS, a continuous gate bias of -20
V was applied for 1000 s. Figs. 3(a) and 3(b) show the transfer and output characteristics of the SG OTFT after a 20 min recovery
period following NGBS. After 1000s of NGBS, a Vth shift of −4.2 V was observed, and upon recovery, Vth shifted by 11.67 V, from −13.6 V to −1.93 V. Under the same NGBS condition, under
the same stress conditions, the drain current decreased from 1.3 µA to −0.8 µA, and
subsequently increased to approximately 1.6 µA after 20 minutes of recovery, exceeding
its initial value. These results indicate that SG OTFTs undergo noticeable characteristic
changes within a relatively short period of time. To examine changes in device characteristics
under bending stress, bending tests of 100, 200, and 300 cycles were performed, and
the transfer and output curves were measured at each step. Figs. 3(c) and 3(d) show the results for a device bent to a radius of 7.05 mm, which was selected as
a representative fixed bending condition within the commonly used 5-10 mm range for
flexible electronics and wearable devices [24,
25]. As the number of bending cycles increased, the on-current at VG = −60 V decreased from 0.7 µA to 0.2 µA, and Vth increased from 13.34 V to 19.7 V. In addition, at VG = −30 V, the drain current decreased from −0.4 µA to −0.1 µA. This degradation is
attributed to a reduction in carrier mobility caused by the applied mechanical stress
[16].
Fig. 3. Negative gate-bias stress (NGBS), recovery behavior, and bending durability
of single-gate (SG) PBTTT OTFTs. (a) Transfer and (b) output characteristics of stress
and recovery behavior of NGBS. (c) Transfer curves after the bending test (100 cycles
step), and (d) output curves.
3. Double-gate PBTTT TFT Characteristics
For parameter extraction, the gate capacitance was determined according to the operating
mode: bottom-gate capacitance (CBG) for bottom-gate operation, top-gate capacitance (CTG) for top-gate operation, and CBG + CTG for dual-gate operation in which both gates contribute simultaneously to channel
modulation.
For DG devices, the electrical performance was compared by defining three operating
modes depending on which gate terminal was biased: TG (VBG = 0), BG (VTG = 0), and DG (VTG = VBG) operation. Figs. 4(a) and 4(b) present the transfer and output characteristics measured under the three operations.
Under DG operation, the on/off ratio was approximately 50× higher than that under
BG operation and ∼10× higher than that under TG operation, and the field-effect mobility
increased by ∼30× and ∼3×, respectively. The DG mode also exhibited the smallest SS,
achieving 3.73 V/dec, compared with 7.41 V/dec and 7.02 V/dec for BG and TG operation,
respectively. Consistently, the DG mode produced the highest drain current, whereas
the BG mode yielded the lowest drain current.
Fig. 4. Double-gate (DG) PBTTT OTFT characteristics under flat and curved conditions
and NGBS. (a) Transfer curves and (b) output curves of the DG OTFT measured under
the flat condition. Transfer curves comparison of the DG OTFTs measured under (c)
flat condition and (d) curved condition. (e) Transfer curve after NGBS. (f) Transfer
curves and (g) output curves of top-gate bias variation with various bottom-gate bias
(VTG: −30-0 V). (h) Transfer curves and (i) output curves of bottom-gate bias variation
with various top-gate bias (VBG: −30-0 V).
Figs. 4(c) and 4(d) compare the performance of a device with W/L = 5000/75 µm under flat and curved conditions.
Measurements were conducted using the same curved jig employed for the SG OTFT evaluation.
Under the curved condition, the DG devices exhibited only limited variation in on-current
and Vth compared with the flat condition. These results demonstrate that, compared with the
SG structure, the DG OTFT provides improved reliability when operated as a flexible
device. For direct comparison, the DG OTFTs were tested under the same NGBS conditions
as the SG OTFTs, with a continuous gate bias of -20 V applied for 1000 s as a representative
moderate bias-stress condition for stability evaluation. The −20 V bias was selected
to represent a moderate electrical stress condition for comparing the SG and DG devices
under the same bias-stress environment, rather than to determine the maximum tolerable
electrical stress. The resulting transfer characteristics are shown in Fig. 4(e). In this case, Vth shifted from 0.8 V to −0.55 V, corresponding to a change of 1.35 V. Because the SG
device exhibited a Vth shift of 7 V under the same stress, the DG device showed an approximately five-fold
smaller Vth variation. This indicates that the DG structure provides improved stability under
stress conditions compared with the SG structure.
A key advantage of the DG OTFT is its voltage-varying capability, whereby the operating
characteristics can be modulated by independently biasing the two gates [17]. To examine this behavior, one gate was held at a fixed voltage while the other gate
was swept. Figs. 4(f) and 4(g) show the transfer and output characteristics obtained under top-gate voltage-sweep
conditions at several fixed VBG, whereas Figs. 4(h) and 4(i) show the corresponding results under bottom-gate voltage-sweep conditions at several
fixed VTG. In both cases, systematic changes in on-current, drain current, and Vth were observed as a function of the fixed gate bias. These results suggest that DG
OTFTs are promising for flexible analog-circuit applications, where tunable device
characteristics under bending conditions are required. These results indicate that
the DG structure offers additional electrical tunability of the drain current and
threshold voltage [26].
The parameter differences between SG and DG operation were compared as a function
of channel length. Fig. 5(a) compares the variation in Vth. Among the three operating modes, BG operation exhibited the highest Vth, whereas DG operation yielded the lowest Vth. Fig. 5(b) compares the field-effect mobility. Consistent with the Vth trend, the lowest mobility was observed under BG operation, while DG operation achieved
approximately two-fold higher mobility than TG operation. Fig. 5(c) compares the on/off ratio, showing that BG operation resulted in the lowest on/off
ratio, whereas DG operation provided the highest on/off ratio
Fig. 5. Parameter comparison of SG and DG OTFT with channel length variation, and
threshold voltage shift after NGBS. (a) Threshold voltage, (b) mobility, (c) on/off
ratio of top single-gate (TG), bottom single-gate (BG), and double-gate (DG). (d)
NGBS-induced threshold voltage shift comparing SG and DG devices.
Fig. 5(d) compares the Vth shift as a function of NGBS time for SG and DG devices. For the SG device, a rapid
negative shift of approximately −10 V within 300 s, followed by a further shift to
−11 V. In contrast, the DG device exhibited a modest Vth shift of about 1.7 V up to 500 s, with no additional Vth change thereafter. These results confirm that DG operation delivers better performance
in terms of Vth, mobility, and on/off ratio compared with TG and BG operation, and that the DG structure
provides significantly improved stability under NGBS conditions relative to the SG
structure. Such performance improvements may be attributed to the enhanced channel
controllability achieved through the use of both top and bottom gates. In addition,
simultaneous biasing of the top and bottom gates may help balance charge trapping
in the top and bottom gate insulators, which could be attributed to the improved operational
stability.
IV. CONCLUSIONS
In this study, PBTTT-channel OTFTs were fabricated on Parylene-C substrates with SG
and DG structures, and their performance and reliability were systematically compared.
To assess stability under electrical and mechanical stress conditions, NGBS and bending
tests were conducted. The DG structure was demonstrated to preserve device performance
more robustly than the SG counterpart under both stress environments.
With the DG configuration, the on/off ratio increased by approximately one order of
magnitude, and the field-effect mobility improved by ∼30× compared with the SG device.
In particular, the DG device exhibited a smaller Vth shift under NGBS than the SG device, indicating enhanced bias-stress stability. This
improvement is attributed to the ability of the dual gates to more precisely modulate
the channel charge distribution, thereby mitigating stress-induced perturbations and
enabling more stable operation. The improved electrical characteristics of the DG
OTFT are likely associated with enhanced electrostatic control and more effective
modulation of charge accumulation in the channel by the double-gate structure.
Furthermore, the DG device enables voltage-varying operation, in which different biases
applied to the two gates allow active tuning of Vth and the on-current. This tunability suggests that DG OTFTs can be a promising platform
for applications requiring controllable and reliable operation under bending, such
as flexible analog circuits and wearable sensors.
ACKNOWLEDGEMENTS
This work was supported by the 2025 Research Fund of the University of Seoul. The
fabrication facility was supported by the Center for Semiconductor Research at the
University of Seoul.
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Ah-Hyun Hong received her B.S. and M.S. degrees from the School of Electrical and
Computer Engineering (ECE) from the University of Seoul in 2022 and 2024, respectively.
Her research interests include the design, fabrication, and characterization of organic,
oxide thin film transistor and biocompatible devices.
Hyungjun Choi received his B.S. and M.S. degrees from the School of Electrical and
Computer Engineering (ECE) from the University of Seoul in 2021 and 2024, respectively,
where he is currently pursuing a Ph.D. degree. His research interests include the
design, fabrication, and characterization of thin film transistor and biocompatible
electrodes.
Kyeungbin Kim received her B.S. degree from the School of Electrical and Computer
Engineering (ECE) from the University of Seoul in 2024, where she is currently pursuing
an M.S. degree. Her research interests include the design, fabrication, and characterization
of thin film transistor and charge trap flash memory.
Dong-Wook Park is a Professor at the University of Seoul in the School of Electrical
and Computer Engineering. He received his Ph.D. degree from the University of Wisconsin-Madison
and got a postdoctoral training at Stanford University, where he studied implantable
neural electrodes and biosensors. Prior to his Ph.D., he was at Samsung SDI and Samsung
Display as an AMOLED circuit design engineer from 2007 to 2011. His current research
centers on emerging biomedical devices and flexible electronics based on novel materials
and nanotechnology.