1. Architecture

The proposed PLL adopts a counter-assisted DPLL architecture, as illustrated in Fig. 1. Unlike conventional fractional-N designs that rely on a delta-sigma modulator (DSM) for frequency division, this approach does not require a DSM, thereby avoiding the generation of high-frequency quantization noise and eliminating the need for additional noise-cancellation circuits. In this loop, the counter together with the TDC converts the DCO frequency into a digital code, generating the frequency command word (FCW) ^[6]. The FCW is then compared with the target code, and the resulting difference is accumulated to obtain the phase error, which is suppressed by the loop through feedback. The overall architecture also includes an accumulator, a digital loop filter (DLF), and a DCO. Fig. 2 illustrates the architecture of the proposed digital PLL. A 3-stage current-controlled ring-DCO is employed as the oscillator core, and a dithering block is used to enhance its effective frequency resolution. A retimer resamples the reference clock CKREF using the DCO output to ensure proper sampling of the counter values. To support multi-GHz operation, a high-speed latch-based counter is adopted in place of a conventional synchronous counter. Within this framework, the proposed TA-based TDC further increases the resolution by sampling the loop counter, achieving fine time-to-digital conversion without the need for additional delay elements.

Fig. 1. Conventional counter-assisted digital PLL.

Fig. 2. Proposed digital PLL with TA-based TDC.

2. Proposed Time Amplifier-based TDC

Fig. 3 illustrates the proposed TA-based TDC, which reuses the loop counter in a counter-assisted DPLL to achieve fine resolution without relying on additional delay elements. The structure begins with a 7-bit rotational counter driven by the DCO output, while a retimer generates the sampled reference clock, CKR. The counter value sampled by CKR, referred to as CNT, is required by the counter-assisted DPLL architecture, as it is forwarded to a differentiator to form the FCW. The input to the TA is derived by exploiting the phase relationship between the DCO and the reference clock. Since CKR is produced by sampling the reference clock with the DCO output, the XOR operation between CKR and CKREF yields a waveform proportional to the residual timing error. To suppress the undesired transitions at the falling edges of CKREF, an additional AND gate is introduced as a filtering stage. Although CKR carries a small offset due to the inherent sampling nature of the retimer, this offset can be digitally calibrated and subtracted. The resulting signal, denoted as T_IN, is then applied to the input of the TA. Within the TDC operation, the TA plays a critical role by amplifying the phase residue between the DCO and CKREF. The TA scales the input error by a factor of 2⁵. For instance, if the original residue spans 0 to T_DCO (where T_DCO is the DCO period), the amplified residue extends to 0 to T_DCO $\cdot$ 2⁵. The amplified timing error now corresponds to discrete quantization levels ranging from 0 to 2⁵ times a single DCO cycle, which is equivalent to achieving a resolution of T_DCO/2⁵. After amplification and sampling, the counter provides a second value, which is subtracted from the CNT initially sampled by CKR. The subtraction result represents the final TDC code. In this manner, fine-resolution time-to-digital conversion is realized with only a single TA block, a few logic gates and the existing counter, achieving higher resolution without adding complex structures such as the delay-line. Furthermore, since the proposed TDC operates based on the counting of the DCO, its resolution automatically scales with the DCO period. Within the valid input range of the TA, the TDC range is inherently aligned to a single DCO cycle, thereby eliminating the need for additional gain matching.

Fig. 3. Proposed TA-based TDC.

Fig. 4(a) shows the schematic of the TA, which is composed of a comparator, two capacitors C₁ and C₂, two current sources I₁ and I₂, and switches for current steering and precharging. The time interpolator proposed in ^[7] is used as the structure of the TA. The operation waveforms of the TA are shown in Fig. 4(b). At the beginning of each amplification cycle, both internal nodes V_A and V_B are precharged to VDD to establish identical initial conditions. When the input pulse T_IN arrives, node V_A is rapidly discharged during the pulse duration by the large current source I₁. After the T_IN pulse ends, V_A is held constant, while V_B starts to discharge slowly through the switch clocked by the DCO output, denoted as CLK, and the smaller current source I₂ = I₁/M. Consequently, V_B decreases gradually until the two nodes intersect. At the crossing point of V_A and V_B, the comparator toggles its output. Because the toggling is delayed in proportion to the input T_IN, the TA effectively transforms the input time difference into an amplified output delay, thus realizing time amplification. The gain of the TA is determined by three factors: the current ratio M between I₁ and I₂, the capacitor ratio N between C₁ and C₂, and the duty cycle of the clock controlling the slow discharge path. In practice, the capacitor ratio cannot be made arbitrarily large, as capacitors occupy significant silicon area. Therefore, in this design, the capacitor ratio is set to 2, while the current source ratio is chosen as 8 to achieve sufficient amplification. With these values combined with the duty cycle of the CLK signal, the effective amplification gain becomes 32, which ensures adequate resolution improvement when combined with the counter sampling mechanism.

Fig. 4. (a) Schematic and (b) timing diagram of the TA.

Unlike conventional time amplifiers that rely on transistor parameters such as transconductance to realize time-domain gain, the proposed structure sets its amplification factor through the ratio of current sources and capacitors, providing inherent robustness against PVT variations ^[8]. To further ensure reliable operation, a gain calibration scheme is incorporated by adjusting the current source I₁, which compensates for process-induced mismatch and duty cycle variations. As a result, the overall architecture achieves high resolution, low hardware overhead, and robust operation under possible PVT variations. It should be noted that the input range of the TDC is determined by both the reference clock period and the discharge slope of the V_A node. If the reference clock frequency is excessively high, its on-time may be insufficient to allow proper signal amplification. To ensure that the amplified signal stays within the on-time of the reference clock, the proposed design employs a 40-MHz reference clock, which provides an on-time of 12.5 ns. Accordingly, the amplified T_IN signal–whose duration includes the retiming delay of CKR introduced by the DFF–is designed to remain well within this 12.5-ns interval, thereby guaranteeing correct counter resampling. Conversely, if the T_IN pulse becomes excessively wide, the capacitor C₁ at the V_A node may fully discharge through the large current source I₁ during the pulse duration. In the proposed circuit, the full discharge time of C₁ is approximately 800 ps, and the width of T_IN is carefully constrained to remain within this limit. If C₁ were to be fully discharged, the comparator would no longer be able to detect the crossing event between V_A and V_B, leading to amplification failure. Provided that these conditions are satisfied, automatic gain matching is inherently achieved across the DCO operating range.

3. High-frequency Latch-based Counter

The proposed high-frequency latch-based counter is designed with a hybrid structure in which the lower three bits adopt a conventional synchronous counter topology, while the upper four bits employ the proposed latch-based counter architecture. Tracing the signal path of each stage, the logic for the next stage is generated by detecting the falling edge of the lower-bit counter output, Q_N-1. To achieve this, a negative latch (LN) followed by a positive latch (LP) is used to generate a short pulse whose width matches that of Q_LSB and whose falling edge is aligned with the falling edge of the preceding Q. This design was motivated by the divider implementation in ^[9], where an LN/LP pair is employed. By taking the XOR operation of this short pulse with the current stage output Q_N, the proper input signal D_N for the DFF is obtained. Furthermore, by using Q_LSB for the RN node, unwanted high states in the LP output are suppressed, ensuring correct toggling only when required.

In conventional synchronous counters, each stage consists of a D flip-flop and multiple basic logic gates, with the input logic determined by the outputs of the previous stages. As the counter width increases, the accumulated gate delay grows, and at high operating frequencies the critical path eventually exceeds one clock cycle, leading to counting failure. In contrast, the proposed latch-based counter replaces the accumulated logic delay with a latch-based sampling scheme using the LN/LP pair. The latch pair enables the generation of short pulses whose falling edges are precisely aligned with the falling edge of the preceding Q, while filtering out spurious transitions. This reduces the total logic depth, yielding a faster implementation. The delay paths of the two structures can be summarized as follows: in order to create the input for the MSB counting stage, a conventional 7-bit synchronous counter requires approximately

T_D,GATE $\times$ 7 + T_D,DEF.

On the other hand, the proposed latch-based counter reduces this to:

T_D,GATE $\times$ 3 + T_D,DEF $\times$ 2.

The logic gates were further optimized to minimize inverting stages. Fig. 6 compares the maximum countable frequency of the two counters, both implemented with comparable transistor sizing and configured as 7-bit designs. The proposed latch-based counter achieves correct counting up to approximately 9.5 GHz, whereas the conventional synchronous counter fails beyond 6.5 GHz. This confirms that the achievable counting rate is significantly higher in the proposed structure. The results are obtained from pre-layout simulations, thus the layout parasitics or process mismatch would reduce the maximum frequency. Even so, the structural advantage of the latch-based architecture remains evident.

Fig. 5. Block diagram of the latch-based counter.

Fig. 6. Simulated countable frequency and the power consumption of the proposed and conventional counters.

4. Two-step Differentiation

In a counter-assisted DPLL, the frequency command word (FCW) is obtained by counting the number of DCO rising edges within one reference clock period. As the frequency difference between the DCO and the reference clock increases, the FCW value grows larger. If the number of DCO edges within one reference period exceeds the maximum countable value of the rotational counter, the counter overflows and wraps around, producing an incorrect frequency code after differentiation ^[10]. This issue becomes critical when the reference frequency is relatively low, since more DCO cycles must be captured in a single reference period.

A straightforward solution would be to increase the counter width, thereby extending the dynamic range. However, this approach has drawbacks: a wider counter not only increases hardware cost but also reduces the maximum countable frequency, effectively limiting the operating range of the DPLL. As a result, counter width extension is not an efficient option for high-frequency designs where compactness and operation speed are essential. To overcome this limitation, a two-step differentiation technique is employed. In addition to sampling the counter at the rising edge of the reference clock, the counter is also sampled at the falling edge. The differences between consecutive samples are computed and then added together, effectively dividing the reference period into two sub-intervals. This method essentially doubles the sampling and extends the number of DCO cycles that can be correctly accumulated without requiring extra counter bits.

Fig. 7 illustrates the concept of two-step differentiation. Fig. 7(a) shows the traditional differentiation method, where only one difference is taken between two counter samples. The dotted vertical lines represent the sampling instants of the counter. In this case, when the second sampled value is greater than the first due to counter rotation, it becomes impossible to determine whether the counter simply increased or completed a full rotation within the reference period T_REF, as illustrated in Fig. 7(a). In contrast, Fig. 7(b) presents the proposed two-step differentiation approach. By inserting an additional sampling point between the two reference clock edges, two differences are computed and summed. The combined value reflects whether the counter has undergone a rotation, thereby allowing the correct frequency command to be reconstructed even when the counter wraps around.

Fig. 7. Counter rotation in (a) traditional differentiation and (b) two-step differentiation.

5. TA Analog Calibration

Fig. 8 shows the block diagram of the analog calibration circuit for the TA. Since the gain of the proposed TA is determined by analog components such as current sources and capacitors rather than transistor parameters as in conventional designs, it is relatively robust to PVT variations; nevertheless, sensitivity to PVT variations is still inevitable. To stabilize the gain across different conditions, a digital monitoring and feedback mechanism is introduced. The monitored signal is derived from the difference between the counter sampled by the reference clock and the counter sampled by the TA output, denoted as CNT_DIFF. This value represents the raw digital difference prior to offset removal, and its dynamic range directly reflects the gain of the TA. In other words, the maximum-to-minimum swing of CNT_DIFF corresponds to the effective amplification factor. By observing CNT_DIFF during the calibration phase, the system can adjust the TA's current sources to align the gain with the target range.

Fig. 8. TA gain calibration circuit.

The calibration is implemented using a 16-bit thermometer code. In the circuit, the large constant current source I₁ is placed in parallel with 16 small current sources, each controlled by a switch. By enabling or disabling these small current sources according to the thermometer code, the overall TA gain can be tuned. The procedure operates via a linear, stepwise search: when the PLL loop begins to lock, all thermometer bits are initially set to '1', configuring the TA for maximum gain. If the CNT_DIFF range exceeds the range of the TDC, the calibration logic decreases the thermometer code one step at a time. This process continues until the CNT_DIFF range falls within the desired bounds, at which point the calibration code converges, and the TA gain is properly adjusted.