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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2026-04 (Vol.26 No.02)
  4. 10.5573/JSTS.2026.26.2.141
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REFERENCES

1 
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2 
Tokairin T. , Okada M. , Kitsunezuka M. , Maeda T. , Fukaishi M. , 2010, A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter, IEEE Journal of Solid-State Circuits, Vol. 45, No. 12, pp. 2582-2590DOI
3 
Elkholy A. , Anand T. , Choi W.-S. , Elshazly A. , Hanumolu P. K. , 2015, A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC, IEEE Journal of Solid-State Circuits, Vol. 50, No. 4, pp. 867-881DOI
4 
Kim H. S. , Ornelas C. , Chandrashekar K. , Shi D. , Su P. , Madoglio P. , Li W. Y. , Ravi A. , 2013, A digital fractional-N PLL with PVT- and mismatch-insensitive TDC utilizing equivalent time sampling technique, IEEE Journal of Solid-State Circuits, Vol. 48, No. 7, pp. 1721-1729DOI
5 
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6 
Kim S. , Hong S. , Chang K. , Ju H. , Shin J. , Kim B. , Park H.-J. , Sim J.-Y. , 2016, A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC, IEEE Journal of Solid-State Circuits, Vol. 51, No. 2, pp. 391-400DOI
7 
Chen P. , Chen C.-C. , Shen Y.-S. , 2006, A low-cost low-power CMOS time-to-digital converter based on pulse stretching, IEEE Transactions on Nuclear Science, Vol. 53, No. 4, pp. 2215-2220DOI
8 
Kwon H.-J. , Lee J.-S. , Kim B. , Sim J.-Y. , Park H.-J. , 2014, Analysis of an open-loop time amplifier with a time gain determined by the ratio of bias current, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 7, pp. 481-485DOI
9 
Elkholy A. , Saxena S. , Nandwana R. K. , Elshazly A. , Hanumolu P. K. , 2016, A 2.0-5.5 GHz wide-bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider, IEEE Journal of Solid-State Circuits, Vol. 51, No. 8, pp. 1771-1784DOI
10 
Silva-Pereira M. , Vaz J. C. , 2018, Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs, Electronics Letters, Vol. 54, No. 5, pp. 284-285DOI
11 
Zhong J. , Yang X. , Martins R. P. , Zhu Y. , Chan C.-H. , 2023, A 0.016 mm$^2$ active area 4 GHz fully ring-oscillator-based cascaded fractional-N PLL with burst-mode sampling, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 70, No. 10, pp. 3792-3796DOI
12 
Kang Z.-H. , Liu S.-I. , 2023, A 1.6-GHz DPLL using feed-forward phase-error cancellation, IEEE Journal of Solid-State Circuits, Vol. 58, No. 3, pp. 806-816DOI
13 
Elmallah A. , Zhu J. , Khashaba A. , Megawer K. M. , Elkholy A. , Hanumolu P. K. , 2022, A 3.2-GHz 405 fs$_{rms}$ jitter -237.2 dB FoM$_{JIT}$ ring-based fractional-N synthesizer, IEEE Journal of Solid-State Circuits, Vol. 57, No. 3, pp. 698-708DOI
14 
Lee T. Seong Y. , Hwang C. , Lee J. , Park H. , Lee K. J. , Choi J. , 2020, A 5.5 GHz ring-DCO-based fractional-N DPLL using a time-invariant-probability modulator generating a nonlinearity-robust DTC-control word, Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 270-272DOI