II. PROPOSED CIRCUIT DESIGN
Fig. 1 shows the simplified schematic of the down-conversion mixer with an LO buffer using
the proposed source-degeneration inductor structure which shares the inner diameter
of the source-degeneration inductors. When the differential superposition technique,
which compensates the nonlinearity of the auxiliary transistor with that of the main
transistor, is applied to a mixer circuit, the source inductor for the main transistor
and that for the auxiliary transistor are typically implemented separately, as illustrated
in Fig. 1. As mentioned in the introduction, the spacing between the inductors should be at
least 400 µm to minimize the magnetic coupling effect between the source degeneration
inductors used in the main and auxiliary transistors. This leads to an increased utilization
of silicon area. Therefore, to reduce the silicon area while taking advantage of the
coupling effect between the source inductors used for the main and auxiliary transistors,
we propose a shared source inductor design, where the inner diameter of the source
inductors is common, as shown in Fig. 1, and apply the differential superposition technique.
Fig. 1. Simplified schematic of the down-conversion mixer with LO buffer using the
proposed source-degeneration inductor structure that shares the inner diameter of
the source-degeneration inductors.
Volterra series analysis is conducted to rigorously examine the circuit design approach
based on the derivative superposition technique, specifically including the impact
of inductive coupling between the inductors connected to the main and auxiliary transistors.
Fig. 2 illustrates the simplified small-signal model employed to derive the nonlinearity
equations of the transconductor shown in Fig. 1. The parasitic gate-drain capacitance $C_{gd}$ is neglected to simplify the nonlinearity
analysis. $v_{in}$ denotes the input voltage signal source. $L_1$ and $L_2$ represent
the source-degeneration inductors, and $M$ indicates the mutual inductance between
them. $C_{gs1}$ and $C_{gs2}$ are the gate-to-source capacitances of M$_1$ and M$_2$,
respectively. As shown in Fig. 2, $v_{in}$, $i_1$, and $i_2$ can be expressed using KCL and KVL as follow:
Fig. 2. Simplified small-signal equivalent schematic of the transconductor for nonlinearity
analysis.
where $v_{s1}$ and $v_{s2}$ are expressed as $v_{s1} = j\omega L_1 i_1 - j\omega M
i_2$ and $v_{s2} = j\omega L_2 i_2 - j\omega M i_1$. Using the Volterra series representation,
the gate-to-source voltage $v_{gs1}$ and the drain-source current $i_a$ of the main
transistor M$_1$, as well as the gate-to-source voltage $v_{gs2}$ and the drain-source
current $i_b$ of the auxiliary transistor M$_2$, can be expressed as follows:
where $v_{in}^n$ represents the $n$th power of the voltage source signal, and $A_n(j\omega)$,
$B_n(j\omega)$, $C_n(j\omega)$, and $D_n(j\omega)$ denote the Volterra-series coefficients,
which are linear functions of $n$ frequencies [9]. The Volterra-series coefficients $A_n(j\omega)$ and $C_n(j\omega)$ are obtained
as using Eqs. (1), (2), (3), and (5), as detailed in Appendix A. The corresponding coefficients are given as $g_{1A} =
g_{m1}$, $g_{2A} = \frac{1}{2} g_{m1}'$, $g_{3A} = \frac{1}{6} g_{m1}''$, $g_{1B}
= g_{m2}$, $g_{2B} = \frac{1}{2} g_{m2}'$, $g_{3B} = \frac{1}{6} g_{m2}''$. The parameters
$g_{m1}$ and $g_{m2}$ represent the first-order transconductance of each transistor,
while $g_{m1}'$, $g_{m1}''$, $g_{m2}'$, and $g_{m2}''$ denote the first- and second-order
derivatives corresponding to the nonlinear characteristics of the devices. Accordingly,
$g_{2A}$ and $g_{3A}$ represent the coefficients of the second- and third-order nonlinear
terms, respectively, where the factors $\frac{1}{2}$ and $\frac{1}{6}$ are derived
from the Taylor series expansion.
From Eqs. (3)-(6), the Volterra-series coefficients $B_n(j\omega)$ and $D_n(j\omega)$ is expressed
as
where
$\overline{A_1(j\omega) A_2(j\omega_1, j\omega_2)} = \frac{1}{3} [A_1(j\omega_1) A_2(j\omega_2,
j\omega_3)$
$\quad\quad\quad\quad\quad\quad\quad\quad\quad+ A_1(j\omega_2) A_2(j\omega_1, j\omega_3)$
$\quad\quad\quad\quad\quad\quad\quad\quad\quad+ A_1(j\omega_3) A_2(j\omega_1, j\omega_2)],$
and
$\overline{C_1(j\omega) C_2(j\omega_1, j\omega_2)} = \frac{1}{3} [C_1(j\omega_1) C_2(j\omega_2,
j\omega_3)$
$\quad\quad\quad\quad\quad\quad\quad\quad\quad+ C_1(j\omega_2) C_2(j\omega_1, j\omega_3)$
$\quad\quad\quad\quad\quad\quad\quad\quad\quad+ C_1(j\omega_3) C_2(j\omega_1, j\omega_2)].$
In Fig. 2, the total drain current $i_t$ is expressed as
$i_t = i_a + i_b$
$= H_1(j\omega) \circ v_{in} + H_2(j\omega_1, j\omega_2) \circ v_{in}^2$
$+ H_3(j\omega_1, j\omega_2, j\omega_3) \circ v_{in}^3,$
where Volterra-series coefficient $H_1(j\omega)$ is given by the sum of $B_1(j\omega)$
and $D_1(j\omega)$, while $H_3(j\omega_1, j\omega_2, j\omega_3)$ is obtained as the
summation of $B_3(j\omega_1, j\omega_2, j\omega_3)$ and $D_3(j\omega_1, j\omega_2,
j\omega_3)$.
From Eqs. (9) and (12), $H_3(j\omega_1, j\omega_2, j\omega_3)$ can be expressed as follows:
To reduce the design degrees of freedom, if the terms inside the brackets of Eq. (13) are designed to be identical, the following condition is satisfied:
Moreover, if Eq. (14) is satisfied, $A_1(j\omega)$ and $C_1(j\omega)$ in Appendix A become identical. Therefore,
under the condition given in Eq. (14), Eq. (13) can be expressed as follows.
The third-order intermodulation intercept point (IIP3) at the frequency $2\omega_b
- \omega_a$ can be calculated using the Volterra-series coefficient $H_3(j\omega_1,
j\omega_2, j\omega_3)$, with the condition that $\omega_1 = \omega_b$, $\omega_2 =
\omega_b$, and $\omega_3 = -\omega_a$. When the difference between the adjacent frequencies
$\omega_a$ and $\omega_b$ is small, it can be assumed that $\omega \approx \omega_a
\approx \omega_b$ [10]. The input tone amplitude at the intercept point of the IMD3 response at $2\omega_b
- \omega_a$ with the fundamental response at $\omega_a$ is given by [7].
Complex mathematical analyses using Eq. (15) and (A.3)-(A.6) lead to the following expression for $H_3(j\omega_b, j\omega_b, -j\omega_a)$.
As shown in Eq. (17), the coupling effect between source degeneration inductors influences the linearity
of the transconductance stage. Maintaining the relationship expressed in Eq. (14), as shown in Eq. (16), the design was carried out to enhance linearity by minimizing the final term in
Eq. (17), such that it approaches zero as closely as possible.
Fig. 3(a) shows the layout of inductors L$_1$ and L$_2$ used for the main and auxiliary transistors,
respectively. Fig. 3(b) presents the inductance and coupling coefficient val-
Fig. 3. (a) Layout of the source degeneration inductors L$_1$ and L$_2$, (b) inductance
and coupling coefficient of the source degeneration inductors L$_1$ and L$_2$.
ues obtained through EM simulation for the inductor layout shown in Fig. 3(a). At a frequency of 28 GHz, the coupling coefficient between the two inductors is
0.193, and the inductance values of L$_1$ and L$_2$ are 590 pH and 380 pH, respectively.
The bias voltages (V$_{B1}$ and V$_{B2}$) for the main and auxiliary transistors are
provided by the current mirror bias circuits [5]. To enhance linearity at a low supply voltage without stacking, the transconductance
stage and switching stage are magnetically coupled via the on-chip $2:1$ transformer
T$_1$.