1. Device Definition and Simulation Conditions

The NSFET was implemented using Synopsys Sentaurus TCAD ^[20]. Fig. 1 shows the 3-D and cross-sectional views of a typical 3-sheet NSFET structure. The 3-sheet 3 nm NSFET structural parameters were determined based on ^{[2, 6, 21- 24]}. The equivalent oxide thickness (EOT) reported in the international roadmap for devices and systems (IRDS) was adopted, and the gate height was modeled independently from the source/drain regions to accurately reflect actual device structures. In addition, the channel doping concentrations are 10¹⁶ cm^-3 for N-type and 10¹⁵ cm^-3 for P-type, while the source/drain doping concentrations are 5$\times$10²⁰ cm^-3 for N-type and 10²¹ cm^-3 for P-type. The structural parameters that are used in this study are shown in Table 2. As shown in Fig. 2, calibration was performed on the I-V measurement data of the IBM 3 nm NSFET ^[2] to verify the physical models applied in TCAD. The error was achieved within 1%.

Fig. 1. NSFET device structure: (a) 3D view, (b) Y-axis cross-section, and (c) X-axis cross-section.

Fig. 2. Calibrated I-V curves with measurement data ^[2] in (a) linear scale and (b) log scale.

Using the calibrated TCAD dataset, the BSIM-CMG model parameters were extracted, and the analytical parasitic capacitance models including contact parasitics ^[9] were incorporated into BSIM-CMG to construct the NSFET SPICE model. While the core I-V models are preserved, geometry-dependent parasitic components are explicitly modeled, enabling the proposed framework to achieve high accuracy in circuit-level performance prediction with respect to layout-related parameters such as $W_{sheet}$ and contact configurations.

2. Standard Cell Definition and Optimization Parameters

The standard cells were implemented using Synopsys Custom Compiler ^[27]. All layers used in the 3 nm NSFET layout were referenced from FreePDK3 ^[28]. Based on FreePDK3, the interconnect technology file (ITF) and a subset of design rule parameters were modified to reflect our 3 nm NSFET and to satisfy the 5-track cell height. In this study, the standard cell height is defined as the product of the metal pitch and the number of tracks, and the power and ground rails adopt the buried power rail (BPR) scheme provided by FreePDK3. The design rules are as follows: The BPR is connected to M0A (MOL) through a VBPR (via), and to M0B (BEOL) through a V0A (via). Additionally, M0B is connected to M1 (BEOL) through a V0B (via). The standard cell is composed of sub-metal layers routed in both horizontal and vertical directions. A design is carried out to meet these design requirements and to match the 5-track cell height ^{[29- 31]}. The INV layout using the 3 nm NSFET is shown in Fig. 3 and the design parameters are shown in Table 3. Within the cell height constrained by the number of metal tracks, design parameters that significantly affect parasitic component variations and their ranges were selected. The width and height of interconnects, vias, and contacts, which can affect the performance of standard cells, are fixed to minimum values for each process node and are difficult to modify. Therefore, designers should select design parameters that can be adjusted and have a significant impact on the parasitic components and key performance metrics of the standard cell. The selected design parameters are sheet width ($W_{sheet}$), P/N spacing, and the number of gate fingers ($NF$). First, in the design rules of the developed standard cells, the minimum spacing between BPR and the sheet is 10 nm, and the minimum spacing between P-type and N-type transistors is 22 nm. Therefore, within this range, $W_{sheet}$ can be set to 20-50 nm, and P/N spacing can be set to 22-82 nm. Next, the driving strength is determined by the output load connected during circuit operation, and the output load is set according to fan-out ^[14]. Fan-out 1-4 (FO 1-4) is a value that reflects the typical load condition in general designs, and represents a reasonable and realistic load that is neither too small nor too large. Moreover, it maintains a similar trend even when technology nodes change, making it a suitable key metric for performance predictions for technology scaling and high performance circuit designs. Therefore, the $NF$, which determines the driving strength depending on the output load of the NSFET, is set to 1-4 ^[32].

Fig. 3. INV layout using 3 nm node NSFETs ^[28].

To apply the proposed standard cell optimization method, three basic types of cells (i.e., INV, NAND, and NOR) were selected as representatives ^[33]. For standard cells with more than two connected P- or N-type transistors, an increase in channel width leads to a corresponding increase in the total effective capacitance. As shown in Fig. 4(a), the NAND consists of N-type transistors connected in series. In this configuration, the drain of the first NMOS and the source of the second NMOS form an internal node. Due to the overlapping diffusion and junction capacitances of the two NMOS transistors at this node, the fall delay increases during switching operations ^[34]. While the on-current increases with the channel width, it has been observed that when $W_{sheet}$ exceeds 40 nm, the increase in total effective capacitance outweighs the delay reduction effect. Therefore, the $W_{sheet}$ range of NAND is between 20-40 nm. In contrast, as shown in Fig. 4(b), the NOR cell has P-type transistors connected in series, leading to similar issues to NAND. However, since the diffusion capacitance of P-type transistors is larger than that of N-type transistors ^[6], the delay reduction effect in NOR is more significantly offset than that in NAND ^[34]. Therefore, the $W_{sheet}$ range of NOR is smaller than NAND, which is between 20-35 nm. The range of design parameters for each standard cell is shown in Table 4.

Fig. 4. Schematic diagrams of (a) NAND and (b) NOR.

1. ANN Model for Objective Function

To generate the datasets, the Sobol sampling method was used ^[35]. This method is known to efficiently explore the design space with a minimal number of samples, and it helps in obtaining datasets with various parameters. The performance of the standard cell was evaluated using 135, 256, 512, and 1024 samples extracted through Sobol sampling. After performing parasitic extraction (PEX) using Synopsys StarRC, post-layout simulations were conducted using Synopsys HSPICE to extract rise delay ($t_{pLH}$), fall delay ($t_{pHL}$), propagation delay ($t_p$), and total power ($P$) ^{[36, 37]}. Here, total power is expressed as the sum of static power and dynamic power. The ANN model was trained using 135 samples generated by Sobol sampling. After training, the ANN model created a multi-objective function, and the relationship between input $X$ and output $Y$ was expressed using the transpose matrix of the weights ($W$) and the biases ($b$) as follows:

The ANN objective function model consists of one input layer, two hidden layers with 20 hidden neurons each, and one output layer, as shown in Fig. 5. The number of neurons in each hidden layer was set to 20 because this configuration achieves approximately 99% test accuracy while maintaining a modest model size, as shown in Fig. 6. The input layer is composed of $W_{sheet}$ , P/N spacing, and $NF$, which represent the standard cell structure parameters, while the output layer consists of the performance metrics of the standard cell to be optimized, namely $t_{pHL}$, $t_{pLH}$, $t_p$, and $P$. When determining the size of the ANN model, the amount of training data must be considered. This is because as the number of training data increases, the model size also increases, which in turn raises computational costs and the risk of overfitting. During the data preprocessing stage, the input was scaled using the Min-Max scaler, and the output was logarithmically scaled for learning efficiency. Hyperbolic tangent was used as the activation function and the Adam optimizer was used. In addition, the mean squared error loss function was used to evaluate the model accuracy, and early stopping was implemented to prevent overfitting due to larger epochs.

Fig. 5. Architecture of the proposed ANN-based objective function model.

Fig. 6. Test error according to the ANN model size.

To evaluate the test accuracy, we gradually increased the training data from 8 to 135 samples using the Sobol sampling method. The results are shown in Fig. 7(a), where the accuracy reached 99% when 135 samples were used. The training and test datasets consisted of 135 Sobol sampling data points and 30 random samples, respectively, and the simulation ran for 30,000 iterations ^[38]. Fig. 7(b) shows the average loss incurred when the trained ANN model makes predictions on a validation dataset that was not used in the training process. This is used to evaluate whether the model is overfitting the training data. It can be observed that as the number of iterations increases, the validation loss decreases, indicating that the ANN model used in this study achieves higher accuracy on the validation dataset. To accelerate the training, the NVIDIA Titan XP GPU was used, and it was confirmed that the ANN model completed training in about 2 minutes. Fig. 8 compares the accuracy between the trained ANN data and the data obtained through simulation, achieving an accuracy of over 98.5%. In this study, standard cells that satisfy a rise and fall delay ratio of 1:1 were designed with the objective of minimizing the propagation delay (high performance) and total power (low power) based on the design goals. This objective can be expressed as follows.

Fig. 7. (a) Test accuracy according to the number of training data with Sobol sampling and (b) validation loss according to epoch.

Fig. 8. Accuracy of the ANN-based objective function model for NAND cells: (a) propagation delay and (b) total power, compared against SPICE simulation.

2. MOBO Model for Optimization

We optimized the standard cell performance using the MOBO model, which efficiently balances multiple performance metrics with high prediction accuracy using a small number of samples. By leveraging a Gaussian process-based probabilistic model and an acquisition function, MOBO selects informative accelerate convergence. It effectively predicts the Pareto frontier and iteratively refines designs.

The MOBO model uses a Gaussian process regression (GPR) model ^[38]. The GPR model represents the relationship between the standard cell structure parameters and performance, considering the uncertainty of the objective function expressed by the variance of the new predicted data. Furthermore, it models the uncertainty between the initial training dataset and the currently explored dataset, and after selecting new samples, it identifies the standard cell structure that maximizes the hypervolume using the acquisition function. Finally, the constraint function is applied to filter out the optimal standard cell structures that do not satisfy the 1:1 rise and fall delay ratio. The algorithm uses the parallel noise-expected hypervolume improvement (qNEHVI) acquisition function of the Botorch package for parallel processing of MOBO to determine the next candidate ^[39]. The output corresponding to the explored input points is interpreted by the ANN objective function model. As a result, the input-output design space is updated by the GPR model. This process is repeated for the defined 80 optimization iterations. The function selects the next data point whose hypervolume is significantly improved compared to the reference point in the MOBO process. Here, the hypervolume is used as a performance metric for Bayesian optimization, which allows for a wider exploration of the objective function space ^[38].

1. Standard Cell Results

We compared the performance of standard cells optimized using the Sobol sampling method with that optimized using the MOBO model. Conventional performance optimization methods, based on different design rules and layer structures, are excluded from comparison ^{[14, 40]}. Fig. 9 shows the hypervolume for the acquisition function, indicating that the optimization process converges sufficiently after 80 iterations. Fig. 10 shows the change in the optimal values explored within the design space as the number of simulation samples increases. A larger number of samples is needed to explore the optimal values. However, as the number of samples increases beyond 1024, the optimal point almost converges. Therefore, we set the optimal number of simulation samples to 1024 using the Sobol sampling method. The constraint was set to ensure a rise and fall delay ratio of 1:1. Data that did not satisfy the constraint were excluded from the candidate group for the MOBO process iterations.

Fig. 9. Hypervolume evolution of the MOBO acquisition function for (a) high performance and (b) low power applications.

Fig. 10. Optimal values according to the number of simulation samples: (a) Propagation delay and (b) total power.

Fig. 11 shows the distribution of optimal points satisfying the constraints for each design objective of NAND obtained using Sobol sampling-based simulation and the MOBO model. While the simulation-based approach required 1024 samples to reach optimal solutions, the MOBO model achieved better results with only 135 samples. As a result, MOBO identified 6, 4, 5, 2, 4, and 2 additional valid design points within the optimal space for INV HP/LP, NAND HP/LP, and NOR HP/LP, respectively. Tables 5 and 6 show the optimal structural parameters, performance, and required sample numbers. First, the structures optimized by the proposed MOBO framework generally exhibit smaller $W_{sheet}$ and appropriately adjusted P/N spacing compared with the simulation-based optimal structural parameters, while the required drive strength tends to be compensated by adjusting $NF$. For example, in the HP INV case, the PMOS and NMOS $W_{sheet}$ values are reduced from 30/30 nm to 20/20 nm, and the P/N spacing is increased from 41 nm to 76 nm, whereas the NMOS $NF$ is increased from 3 to 4. This configuration reduces the gate, diffusion, and junction capacitances at the P/N boundary by increasing the P/N spacing, while maintaining sufficient drive current through the increased $NF$, thereby reducing the propagation delay of the HP INV by approximately 23.2%. In the LP application, the proposed MOBO framework mainly selects structures that minimize power by shrinking the $W_{sheet}$ of transistors connected in series in NAND/NOR cells to suppress diffusion capacitance at internal nodes, and by adjusting the P/N spacing. As a result, it achieves up to 10.3% reduction in power for the LP NAND case compared with the simulation-based optimal structural parameters.

Fig. 11. Comparison of optimized NAND cell performance: (a) high performance mode and (b) low power applications.

We further performed a Spearman correlation analysis to investigate how the explored directions of the optimal structural parameters obtained from the proposed MOBO framework affect delay and power. The Spearman correlation is a metric that can quantify the importance of nonlinear relationships between input and output variables ^[41]. As shown in Table 7, the propagation delay of the three cells (INV, NAND, and NOR) exhibits a positive correlation with the PMOS and NMOS $W_{sheet}$ , whereas it shows a negative correlation with P/N spacing, PMOS $NF$, and NMOS $NF$. This quantitatively supports that an excessive increase in $W_{sheet}$ leads to an increased cell propagation delay, while widening the P/N spacing or appropriately adjusting $NF$ is more effective in reducing propagation delay. For power, the correlation coefficients between power and NMOS $NF$ are 0.67, 0.73, and 0.85 for INV, NAND cells, and NOR, respectively, indicating that an increase in NMOS $NF$ is a dominant factor that increases total power consumption.

Fig. 12 shows the rise and fall delays of the final standard cells designed using optimized INV, NAND, and NOR. In the cases of NAND and NOR HP, the rise and fall delay ratios are improved by 15.8% and 18.7%, respectively. Since complex standard cells (i.e., XOR, AOI, OAI, DFF, etc.) consist of a combination of INV, NAND, and NOR, optimization can be well achieved. In addition, the rise and fall delay ratios of more complex standard cells are improved. Therefore, MOBO can optimize the rise and fall delay ratios of various standard cells to be much closer to 1:1 compared to simulation-based approaches. Fig. 13 compares the performance of various standard cells. MOBO showed significantly better performance optimization results than simulation-based optimization, resulting in improved performance optimization for a variety of standard cells. The simulation took 40 minutes for 80 iterations on a computer with an Intel Core i9-7900X CPU.

Fig. 12. Comparison of standard cell rise and fall delays.

Fig. 13. Comparison of standard cell performance across optimization methods: (a) propagation delay and (b) total power.

2. Test Circuit Results

To evaluate the optimized standard cells, a 7-stage ring oscillator (RO) and a 4-bit ripple carry adder (RCA) were used as test circuits ^[12]. Total power (LP) and propagation delay and frequency (HP) were measured for the RO, while total power (LP) and propagation delay (HP) were measured for the RCA. The frequency means the oscillation frequency measured during operation ^[42]. The SPICE model was adopted from previous research ^{[9, 25, 26, 43, 44]}. As shown in Table 8, the RO achieved a rise-fall delay ratio close to 1:1, which is about 12% better than the simulation-based design. In addition, for HP, the propagation delay was reduced by 22.9% and the frequency was improved by 29.9%. For LP, the total power was reduced by 19.2%. The performance of the 4-bit RCA designed using various standard cells optimized by simulation-based approach and the MOBO model was also evaluated. For HP, the propagation delay was reduced by 18.6% and for LP, the total power was reduced by 11.9%. Based on these results, we can conclude that not only can timing be symmetrically improved in complex circuits but also overall performance can be significantly improved. Furthermore, performance and power consumption improvements are expected at larger complex circuit levels.