| Title |
Design of High-speed and Low Cost Bitonic Sorting Network |
| DOI |
https://doi.org/10.5573/JSTS.2026.26.2.174 |
| Keywords |
Bitonic sorting network; bit-serial bitonic sorting network; sorting network; odd-even sorting network; bit-serial operation |
| Abstract |
An implementation of bit-serial bitonic sorting network (BBSN) is presented in this paper. While all bits of an input enter sorting network simultaneously, inputs to bit-serial sorting network enter as bit-streams. BBSN uses 1-bit compare and swap (CAS) unit while normal bitonic sorting networks (NBSN) use multi-bit CAS units.
By using a small and fast CAS unit, BBSN can reduce area, power consumption, and latency of NBSN. The size of the BBSN is about 81% of NBSN for 8-bit 8 inputs, and it is about 20% for 8-bit 128 inputs. For 16-bit inputs, it is 17% for 128 inputs. Comparing power consumption of BBSN to NBSN, it consumes 60% of NBSN for 128 of 8-bit inputs, and 40% for 16-bit inputs. The proposed sorting network could be slower than NBSN for small number (N < 32) of wide-bit (m ≥ 16) inputs, but it becomes faster when number of input increases. BBSN is 16% faster than NBSN in sorting 128 of 16-bit inputs, and the percentage grows as the number of inputs increases. The proposed sorting network could be used for many applications which require high-speed sorting operations. |