Heat Dissipation Improvement Using Plugged Sidewall for Three-dimensional (3D) Package
of High-stacked High Bandwidth Memory (HBM)
Eun Pyo Hong1
Sang Won Yoon1,2,*
-
(Department of Electrical and Computer Engineering, Seoul National University, Seoul
08826, South Korea)
-
(Inter-University Semiconductor Research Center, Seoul 08826, South Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
3D package, advanced packaging, finite element analysis (FEA), heat flux, high bandwidth memory (HBM), plugged sidewall, thermal management, thermal stress
I. INTRODUCTION
High Bandwidth Memory (HBM) has emerged as a critical component for high-performance
computing (HPC) systems, enabling advancements in artificial intelligence, scientific
simulations, and data-intensive applications [1]. Among the existing HBM technologies, the three-dimensional (3D) package structures
offer a unique ability to meet the ever-growing demands for ultra-high memory bandwidth,
low latency, high power efficiency, and compact form factors [2]. These characteristics are essential for enabling next-generation HPC systems to
process massive datasets at unprecedented speeds while maintaining energy efficiency
and spatial constraints.
Although 3D integration of the dies enables various advantages, it also introduces
thermal challenges related to thermal management, mechanical stress, and long-term
reliability [3]. 3D integration greatly shortens signal paths and increases density, but it also
amplifies self-heating and creates tight thermal coupling between layers [4]. However, package level heat removal is bottlenecked because most heat from the logic
die must flow upward through the dynamic random access memory (DRAM) stack or laterally
through low thermal conductivity mold compound [5]. As the number of DRAM dies and the power of HBM increases, conventional heat dissipation
methods struggle to keep junction temperatures and overall package temperatures below
reliability limits. Therefore, new heat extraction paths that bypass the stacked DRAM
dies are essential for the next generation, high stacked 3D HBM packages.
To address these issues, there were prior studies relying on using dummy-TSV (Through
Silicon Via) [6], or dummy-bumps located inside the stacked dies [7]. Also, some research focused on adding extra dummy-die above the stacked dies, for
heat dissipation purpose [8]. However, these approaches still create heat dissipation paths within HBM, which
cause limitations on lowering overall package temperature, or fail to relieve HBM
thermal load that worsens as the number of die stacks and the power of HBM increase.
This paper proposes a method of using plugged sidewall surrounding DRAM stack of the
HBM to reduce DRAM die temperature, overall HBM package temperature, and thermal stress
inside the package by enabling heat extraction through additional paths bypassing
the inner regions of the HBM.
II. PROPOSED CONCEPT
To alleviate thermal bottlenecks in 3D HBM package, we propose a novel design by incorporating
an additional hollow rectangular structure, named a plugged sidewall, embedded in
the mold compound region surrounding the stacked DRAM dies of the HBM. Copper was
chosen as the material of the plugged sidewall due to its high thermal conductivity
(~400 W/m·K) [9].
Fig. 1 depicts two structures of 3D HBM packages. The conventional HBM package in Fig. 1(a) places a cold plate on top of the package through a TIM, followed by a DRAM stack
including TSVs and a bottom logic die. The logic die is connected to the substrate
through C4-bumps with underfill. Meanwhile, our proposed structure in Fig. 1(b) keeps the same stacking and interconnect scheme but embeds a plugged sidewall, molded
around the DRAM stack. This sidewall creates additional heat dissipation paths within
the mold compound, reducing the logic die temperature. It also provides mechanical
constraint, mitigating thermal stress concentration near the die corners.
Fig. 1. Cross-sectional (left images) and top side (right images) views of the (a)
conventional 3D HBM package and (b) proposed 3D HBM package structure with plugged
sidewall.
As shown in Fig. 2(a), in the conventional 3D HBM package, most of the heat generated from the logic die
cannot dissipate through the EMC region and is instead conducted through the DRAM
stack, due to the low thermal conductivity of the EMC (~0.8 W/m·K) [5]. On the other hand, as illustrated in Fig. 2(b), newly added plugged sidewall structure creates a direct heat dissipation path that
bypasses the stacked dies, thanks to the high thermal conductivity of the copper.
This increases the effective paths for heat transfer, reducing heat flow inside the
DRAM stack, and lowering the logic die temperature.
Fig. 2. Conceptual views of the heat flow in a (a) conventional 3D HBM package and
(b) proposed 3D HBM package structure with plugged sidewall.
The geometric dimensions of the plugged sidewall were determined through a sequential
design process that prioritizes process reliability and thermal performance. First,
the spacing between the sidewall and the DRAM stack was selected based on reported
process stability guidelines and die-to-metal clearance criteria [10,
11]. Within this spacing constraint, the sidewall width was defined using the maximum
available area on the underlying logic die to enhance heat dissipation, rather than
through independent parametric optimization.
The proposed plugged sidewall was designed with reference to established and well-documented
package-level fabrication processes, with the aim of maximizing process compatibility
and practical feasibility. In particular, the design draws upon representative examples
of mature techniques, such as post-mold laser structuring of epoxy mold compounds
and subsequent copper metallization, which have been widely reported in advanced packaging
studies [12-
17].
Regarding interfacial reliability between the copper plugged sidewall and EMC, it
is well recognized that Cu–EMC interfaces in molded packages can be susceptible to
delamination under thermo-mechanical stress and moisture exposure [18,
19], and therefore require appropriate consideration in design and process integration.
In the proposed structure, however, the plugged sidewall does not introduce a new
material interface but relies on the same Cu–EMC interfaces used in established packaging
technologies such as TMV-based PoP and leadframe packages. Previous studies have shown
that, with standard surface preparation, these interfaces can exhibit robust reliability
under thermal cycling and humidity conditions [18,
20].
III. FINITE ELEMENT ANALYSIS (FEA) SIMULATION RESULTS
1. 3D Modeling
For both the conventional and the proposed 3D HBM package structures shown in Fig. 1, the DRAM die stacks were modelled in 4-dies, 8-dies, 12-dies, and 16-dies HBM configurations.
The terms 4-dies, 8-dies, 12-dies, and 16-dies each indicate that the number of DRAM
dies in a stack is 4, 8, 12, and 16, respectively. Material properties used in the
modeling and simulation were set based on previous studies [9,
21-
24]. All the material properties are summarized in Table 1.
Table 1. Summary of the materials properties used in the simulations.
|
Materials
|
Young's modulus [GPa]
|
Poisson's ratio
|
CTE [10-6/K]
|
Thermal conductivity [W/m·K]
|
|
Silicon
|
170
|
0.28
|
2.6
|
145
|
|
Nickel
|
200
|
0.31
|
13
|
90
|
|
Solder
|
90
|
0.42
|
18
|
58
|
|
Copper
|
70
|
0.34
|
17
|
400
|
|
NCF
|
2.3
|
0.33
|
76
|
0.5
|
|
Underfill
|
1
|
0.38
|
17
|
0.23
|
|
TIM
|
0.15
|
0.4
|
309.6
|
7.62
|
|
FR-4
|
22
|
0.35
|
17
|
In-plane: 0.81
|
|
Out of plane: 0.29
|
|
Epoxy molding compound (EMC)
|
30
|
0.3
|
18.5
|
0.8
|
To accurately capture vertical heat transfer within the DRAM stack, TSVs were explicitly
modeled, as illustrated in Fig. 3(a). The TSV diameter and pitch were selected based on representative values reported
in prior literature [25]. To maintain computational efficiency while preserving thermal fidelity, an equivalent
TSV model was adopted in which the diameter and pitch were proportionally adjusted,
while the total cross-sectional area and effective vertical thermal conductance were
preserved. This modeling approach is consistent with simplification strategies reported
in previous studies [26,
27]. The heat-flux distribution shown in Fig. 3(b) further indicates that the modeled TSVs serve as the primary vertical heat conduction
path within the DRAM stack.
Fig. 3. (a) TSV modeling results within the DRAM stack (top DRAM die removed to show
the TSVs), and (b) heat flux vectors indicating that the majority of heat in the DRAM
stack is conducted upward through TSVs.
Subsequently, 3D FEA simulations using ANSYS Mechanical software were performed to
analyze thermal characteristics, including temperature distribution, the maximum temperature,
overall heat flux paths and thermal stress distribution within the package. For the
thermal stress analysis, we focused on the thermal stress at the logic die, especially
the edge region of the logic die, where most of the thermal stress is concentrated
[5].
2. Thermal Simulation
Fig. 4 shows the thermal simulation results for 3D HBM package structures. Thermal simulations
were performed for 3D HBM packages with 4-dies, 8-dies, 12-dies, and 16-dies stacks
under both the conventional and proposed structures. In all cases, thermal hotspots
were found to be located at the edges of the logic die, consistent with prior thermal
research on 3D HBM packages [28]. This primarily stems from the fact that the die periphery in the edge region concentrates
more power into less area, increasing power density relative to the die center. Additionally,
whereas the central region benefits from a direct conductive path through the HBM
stack to the TIM and cold plate, heat at the edges must largely traverse the low thermal
conductivity molding compound, which is a much poorer thermal pathway.
Fig. 4. Thermal simulation results for (a) the conventional 3D HBM package and (b)
the proposed 3D HBM package with a plugged sidewall, showing the temperature distribution
and the corresponding maximum package temperature.
For the conventional 4-dies HBM structure in Fig. 2(a), the peak package temperature at the hotspot reached 108.1°C, as shown in Fig. 4(a). As the number of DRAM dies in the stack increased to 8, 12 and 16, the temperature
rose to 110.6°C, 113.0°C and 115.4°C, respectively. However, when a plugged sidewall
was added to the package, the maximum package temperature dropped to 92.6°C (~14.3%
reduction) for the 4-dies case. Similar trends were observed for the other configurations,
as summarized in Fig. 4 and Table 2.
Table 2. Summary of the thermal simulation results for 4-dies, 8-dies, 12-dies, and
16-dies 3D HBM packages.
|
Number of DRAM dies in HBM
|
Conventional 3D HBM package
|
Proposed 3D HBM package structure with plugged sidewall
|
|
Package max. temp. [°C]
|
Package max. temp. [°C]
|
|
4
|
108.1
|
92.6 (14.3%↓)
|
|
8
|
110.6
|
94.9 (14.2%↓)
|
|
12
|
113.0
|
97.4 (13.8%↓)
|
|
16
|
115.4
|
99.8 (13.5%↓)
|
The results confirms that the improvement was consistent across all stack heights.
This indicates that the plugged sidewall greatly strengthened the heat-removal path
from the logic die to the top side, suppressing local hot spots while also effectively
lowering the overall package temperature. Furthermore, these results show that, even
as stack height increases, the proposed structure robustly enhances thermal management
of the 3D HBM packages.
Moreover, Fig. 4 shows that the location of the maximum temperature differs between the conventional
and proposed structures. This behavior originates from the asymmetric placement of
the DRAM stack on the underlying logic die, as reported in prior studies [28,
29]. In the conventional structure, the maximum temperature appears on the side with
the wider EMC region, where lateral heat dissipation is relatively limited due to
the low thermal conductivity of the mold compound. In contrast, in the proposed structure,
the wider EMC region incorporates a correspondingly wider copper plugged sidewall,
providing an enhanced lateral heat conduction path. As a result, the maximum temperature
shifts toward the opposite side with the narrower EMC region, where the plugged sidewall
is thinner and offers comparatively lower heat dissipation.
To verify whether the heat actually flowed through the plugged sidewall as intended,
we performed heat flux simulations and observed the resulting heat dissipation paths.
The simulation results are revealed in Fig. 5. In the conventional HBM package structures (Fig. 5(a)), the available paths for heat from the logic die to dissipate were mainly through
the DRAM stack or the mold compound. However, since the mold compound has significantly
lower thermal conductivity than other components, the effective heat dissipation path
was essentially constrained inside of the stacked DRAM, which enforces a limited thermal
strategy. In the mold compound region highlighted by the black box in Fig. 5(a), little to no heat flux can be observed compared with the DRAM stack region. In contrast,
Fig. 5(b) highlights that with the insertion of the plugged sidewall into the mold region,
additional heat dissipation paths were created. As a result, the heat from the logic
die could bypass the DRAM stack and dissipate through the plugged sidewall. The red-highlighted
area in Fig. 5(b) shows that a substantial heat flux is now present in the mold compound region, where
almost no heat flow had previously exhibited.
Fig. 5. Heat flux simulation results for the (a) conventional 3D HBM packages and
(b) proposed 3D HBM package structures with plugged sidewall, illustrating heat dissipation
within the package.
3. Thermo-mechanical Simulation
Since the thermal hotspot temperature at the logic die edges decreased and the overall
package temperature dropped, a reduction in thermal stress throughout the package
is also expected as an additional benefit of these thermal improvements. Therefore,
thermal stress analysis was conducted for both the conventional and proposed structures,
and the results were compared.
Figs. 6 and 7 present the thermo-mechanical simulation results, showing the thermal stress distribution
in the logic die and localized stress concentrations around TSVs, respectively. As
widely reported for 3D stacked die structures, thermal stress is highest at the die
edges [5,
30], and Fig. 6 likewise shows elevated stress at the corners of the logic die in the 3D HBM package.
Localized thermal stress concentrations are also observed near TSVs, as shown in Fig. 7. Since such near-TSV stress concentrations are highly sensitive to local geometry
and process variations [31,
32], the present study focuses on the comparative thermal stress behavior of the logic
die. Accordingly, the average thermal stress at the four corners of the logic die
was extracted and compared.
Fig. 6. Thermo-mechanical simulation results for the (a) conventional 3D HBM packages
and (b) proposed 3D HBM package structures with plugged sidewall, depicting thermal
stress distributions of the logic die.
Fig. 7. Thermal stress distribution around TSVs in the conventional 3D HBM package,
illustrating localized stress concentrations in the vicinity of the vias.
The comparison results are presented in Fig. 6 and Table 3. Although the average stress rises with increasing stacked-die numbers for both structures,
the proposed package structure yields lower average stress than the conventional structure
for all stack heights. Furthermore, the proposed structure exhibits a more gradual
rise with the increasing number of stacked dies. Thermal stress values at all four
corners were also measured to have decreased in the proposed structure, compared to
the conventional design.
Table 3. Summary of the thermo-mechanical simulation results for 4-dies, 8-dies, 12-dies,
and 16-dies 3D HBM packages.
|
Number of DRAM dies in HBM
|
Conventional 3D HBM package
|
Proposed 3D HBM package structure with plugged sidewall
|
|
Average thermal stress at four corners of logic die [MPa]
|
Average thermal stress at four corners of logic die [MPa]
|
|
4
|
545.5
|
366.7 (32.8%↓)
|
|
8
|
583.5
|
391.7 (32.9%↓)
|
|
12
|
675.6
|
432.2 (36.0%↓)
|
|
16
|
746.4
|
466.6 (37.5%↓)
|
When the exact average values are compared between the conventional and proposed designs,
the reductions are 32.8%, 32.9%, 36.0%, and 37.5% for the 4-dies, 8-dies, 12-dies,
and 16-dies structures, respectively, demonstrating consistent improvements across
all configurations. Notably, the reduction exceeds 36% for the 12-dies and 16-dies
cases, indicating that the benefit of the proposed structure becomes more pronounced
as stack height increases. These results suggest that the proposed design more effectively
mitigates corner-dominated thermal stress as stack height increases, making it especially
attractive for high-stack HBM packages.
These reductions in the average thermal stress at the four corners of the logic die
are potentially achieved by the thermal and mechanical factors. A decrease in the
overall package temperature ultimately had a positive effect on lowering thermal stress,
since the magnitude of thermal stress is largely governed by the temperature distribution
and thermal load [33]. From a mechanical standpoint, the copper plugged sidewall acts as a mechanical constraint
to the logic die, thereby providing structural reinforcement and mitigating thermal
stress. Introducing mechanical constraint or local reinforcement at high-stress locations
on the die, offers a practical benefit for mitigating thermal stress [34]. Moreover, since a high Young's modulus of the EMC material helps mitigate thermal
stress in the die [35], embedding copper (with a Young's modulus over twice that of the EMC) into the EMC
region will increase the region's effective Young's modulus and, as a result, has
a positive impact on thermal stress profile of the logic die.
IV. CONCLUSION
In this study, we have demonstrated that embedding a plugged sidewall around the DRAM
stack within the EMC region, provides an effective bypass for heat and additional
mechanical constraint for the 3D HBM package with different DRAM stack heights. 3D
FEA simulation results confirmed that the newly proposed package structure reduced
maximum hotspot package temperature, and thermal stress formation on the logic die.
Heat flux analysis showed that the added plugged sidewall effectively creates new
heat dissipation paths that divert heat from the logic die away from the stacked DRAM,
thereby reduces both the overall package temperature and in-stack thermal load.
Across 4-dies, 8-dies, 12-dies, and 16-dies configurations, simulation results showed
consistent thermal benefits, with the package maximum temperature reduction about
14% for all cases. The proposed design also mitigated thermo-mechanical risks, lowering
the average thermal stress at the four corners of the logic die by more than 32%,
with 37.5% maximum reduction in 16-dies case. These results indicate that the plugged
sidewall expands thermal headroom while alleviating corner-dominated thermal stress,
making it a strong candidate for reliable higher-stack 3D HBM packages. Our study
provides thermal management techniques for next-generation 3D HBM packages, and guidelines
for thermal analysis methodology of vertically stacked die structures.
ACKNOWLEDGEMENTS
This work was supported by Korea Planning & Evaluation Institute of Industrial Technology
(KEIT) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea)(RS-2025-02305881,
PSU Development based on GaN·SiC Transfer Molded Module) and Korea Institute for Advancement
of Technology(KIAT) grant funded by the Korea Government(MOTIE) (RS-2025-02214408,
HRD Program for Industrial Innovation).
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Eun Pyo Hong received his B.S. degree in electronic engineering from the Kyunghee
University, South Korea in 2024. He is currently working toward a unified master's
and doctor's degrees with the Department of Electrical and Computer Engineering, Seoul
national University, Seoul. His current research interests include advanced packaging
and power module packaging.
Sang Won Yoon received his B.S. degree in electrical engineering from Seoul National
University, Seoul, South Korea, in 2000, and his M.S. and Ph.D. degrees in electrical
engineering and computer science from the University of Michigan, Ann Arbor, MI, USA,
in 2003 and 2009, respectively. From 2009 to 2013, he was a Senior Scientist and a
Staff Researcher with the Toyota Research Institute of North America, Ann Arbor, where
he conducted research in the fields of power electronics and sensor systems for automobiles.
From 2013 to 2023, he was an Assistant Professor, an Associate Professor, and a Professor
with the Department of Automotive Engineering, Hanyang University, Seoul. Since 2023,
he has been with the Department of Electrical and Computer Engineering, Seoul National
University. His current research interests include packaging and reliability of semiconductors,
sensor systems, and their applications.