Mobile QR Code QR CODE

References

1 
L. Wilson, International Technology Roadmap for Semiconductors (ITRS). Washington, DC, USA: Semiconductor Industry Association, 2013. [Online]. Available: https://www.semiconductors.orgURL
2 
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, ``Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories,'' Proc. DAC, pp. 1-6, Jun 2016.DOI
3 
T. Na, ``Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing,'' IEEE Trans. Circuits Syst. II, Exp., vol. 70, no. 7, pp. 2655-2659, Jul. 2023.DOI
4 
P.-H. Lee et al., ``33.1 A 16nm 32Mb embedded STT-MRAM with a 6ns read-access time, a 1M-cycle write endurance, 20-year retention at 150$^\circ$C and MTJ-OTP solutions for magnetic immunity,'' Proc. of 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 494-496, 2023.DOI
5 
Z. Xiao et al., ``Device variation-aware adaptive quantization for MRAM-based accurate in-memory computing without on-chip training,'' Proc. of 2022 International Electron Devices Meeting (IEDM), pp. 10.5.1-10.5.4, 2022.DOI
6 
M. Hosomi et al., ``A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM,'' IEEE IEDM Tech. Dig., pp. 459-462, Dec. 2005.DOI
7 
S. Ikeda et al., ``A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction,'' Nature Mater., vol. 9, pp. 721-724, Jul. 2010.DOI
8 
R. Takemura et al., ``A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and `1'/`0' dual-array equalized reference scheme,'' IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 869-879, Apr. 2010.DOI
9 
C. Wang, Z. Wang, G. Wang, Y. Zhang, and W. Zhao, ``Design of an area-efficient computing in memory platform based on STT-MRAM,'' IEEE Transactions on Magnetics, vol. 57, no. 2, pp. 1-4, Feb 2021.DOI
10 
S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, ``Computing in memory with spin-transfer torque magnetic RAM,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470-483, March 2018.DOI
11 
J. Yu, G. Lee, and T. Na, ``High-performance sum operation with charge saving and sharing circuit for MRAM-based in-memory computing,'' IEIE J. Semicond. Technol. Sci. (JSTS), vol. 22, no. 2, pp. 111-121, Apr. 2024.DOI
12 
T. Na, J. Kim, J. P. Kim, S. H. Kang, and S.-O. Jung, ``Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 12, pp. 3376-3385, Dec. 2014.DOI
13 
T. Na, B. Song, J. P. Kim, S. H. Kang, and S.-O. Jung, ``Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65 nm CMOS,'' IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 496-504, Feb. 2017.DOI
14 
G. P. Devaraj, R. Kabilan, J. Z. Gabriel, U. Muthuraman, N. Muthukumaran, and R. Swetha, ``Design and analysis of modified pre-charge sensing circuit for STT-MRAM,'' Proc. of 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV), Tirunelveli, India, pp. 507-511, 2021.DOI
15 
T. Na, S. H. Kang, and S.-O. Jung, ``STT-MRAM sensing: A review,'' IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 1, pp. 12-18, Jan. 2021.DOI
16 
G. Wang et al., ``Compact modeling of perpendicular-Mmagnetic-anisotropy double-barrier magnetic tunnel junction with enhanced thermal stability recording structure,'' IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2431-2436, May 2019.DOI
17 
T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, ``Multiple-cell reference scheme for narrow reference resistance distribution in deep submicrometer STT-RAM,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 9, pp. 2993-2997, Sep. 2016.DOI