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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

1 
Park J., Hwang Y., Jeong D., 2019, A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors, IEEE Access, Vol. 7, No. , pp. 63686-63697DOI
2 
Fateh S., Schonle P., Bettini L., Rovere G., Benini L., Huang Q., 2015, A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 11, pp. 2685-2694DOI
3 
Moon S., Kim I., Kam D., Jee D., Choi J., Lee Y., 2019, Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance, IEEE Access, Vol. 7, No. , pp. 6650-6660DOI
4 
Xu R., Liu B., Yuan J., 2012, Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering, IEEE Journal of Solid-State Circuits, Vol. 47, No. 9, pp. 2129-2140DOI
5 
Shu Y., Kuo L., Lo T., 2016, An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, pp. 2928-2940DOI
6 
Ding M., Harpe P., Liu Y., Busze B., Philips K., Groot H. d., 2017, A 46 uW 13b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration, IEEE Journal of Solid-State Circuits, Vol. 52, No. 2, pp. 423-432DOI
7 
Yoshioka M., Ishikawa K., Takayama T., Tsukamoto S., 2010, A 10-b 50-MS/s 820-uW SAR ADC With On-Chip Digital Calibration, IEEE Transactions on Biomedical Circuits and Systems, Vol. 4, No. 6, pp. 410-416DOI
8 
Nikolic D. Stepanovic and B., 2013, A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 48, No. 4, pp. 971-982DOI
9 
Ji-Yong U., Yoon-Jee K., Eun-Woo S., Jae-Yoon S., Hong-June P., 2013, A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits, Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 60, No. , pp. 2845-2856DOI
10 
Liu W., Huang P., Chiu Y., 2011, A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration, IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, pp. 2661-2672DOI
11 
Zhu Y., Chan C., Chio U., Sin S., S U., Martins R. P., Maloberti F., 2014, Split-SAR ADCs: Improved Linearity With Power and Speed Optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 2, pp. 372-383DOI
12 
Zhu Y., Chan C., Wong S., Seng-Pan U., Martins R. P., 2016, Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 3, pp. 1203-1207DOI
13 
Giannini V., Nuzzo P., Chironi V., Baschirotto A., Plas G. V. d., Craninckx J., 2008, An 820${\mu}$W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS, in IEEE International Solid-State Circuits Conference - Digest of Technical Papers, Vol. , No. , pp. 238-610DOI
14 
Harpe P., Cantatore E., Roermund A. v., 2013, A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step, IEEE Journal of Solid-State Circuits, Vol. 48, No. 12, pp. 3011-3018DOI
15 
Miki T., Morie T., Matsukawa K., Bando Y., Okumoto T., Obata K., Sakiyama S., Dosho S., 2015, A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques, IEEE Journal of Solid-State Circuits, Vol. 50, No. 6, pp. 1372-1381DOI
16 
Yeo I., Kim B., Chu M., Lee B., 2014, Digital foreground calibration of capacitor mismatch for SAR ADCs, Electronics Letters, Vol. 50, No. 20, pp. 1423-1425DOI
17 
Chang A. H., Lee H., Boning D., 2013, A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration, in Proceedings of the ESSCIRC (ESSCIRC), Vol. , No. , pp. 109-112DOI
18 
Park C., Kim W.-T., Yeo I.-J., Jeon M., Lee B.-g., 2019, An event detection module with a low-power, small-size CMOS image sensor with reference scaling, Analog Integrated Circuits and Signal Processing, Vol. 99, No. 2, pp. 359-369DOI
19 
Kim J., Leibowitz B. S., Ren J., Madden C. J., 2009, Simulation and Analysis of Random Decision Errors in Clocked Comparators, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 8, pp. 1844-1857DOI
20 
Fernandes T. Rabuske and J., tion 2014, Noise-aware simulation-based sizing and optimization of clocked comparators, Analog Integrated Circuits and Signal Processing, Vol. 81, No. 3, pp. 723-728DOI
21 
Namgoong M. Ahmadi and W., 2015, Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 11, pp. 2384-2394DOI
22 
Tong W. P. Zhang and X., 2015, Noise Modeling and Analysis of SAR ADCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 12, pp. 2922-2930DOI
23 
Cho S., Lee C., Kwon J., Ryu S., 2011, A 550-uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction, IEEE Journal of Solid-State Circuits, Vol. 46, No. 8, pp. 1881-1892DOI
24 
Sadollahi M., Hamashita K., Sobue K., Temes G. C., 2018, An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 1, pp. 61-73DOI
25 
Zhu Y., Chan C., Chio U., Sin S., S U., Martins R. P., Maloberti F., 2010, A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 45, No. 6, pp. 1111-1121DOI
26 
Yavari E. Rahimi and M., 2014, Energy-efficient high-accuracy switching method for SAR ADCs, Electronics Letters, Vol. 50, No. 7, pp. 499-501DOI
27 
Hsu C., Chang S., Huang C., Chang L., Shyu Y., Hou C., Tseng H., Kung C., Hu H., 2018, A 12-b 40-MS/s Calibration-Free SAR ADC, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 3, pp. 881-890DOI
28 
Martens E., Hershberg B., Craninckx J., 2018, A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization, IEEE Journal of Solid-State Circuits, Vol. 53, No. 4, pp. 1161-1171DOI
29 
Haenzsche S., Hoppner S., Ellguth G., Schuffny R., 2014, A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 835-839DOI