| Title |
[REGULAR PAPER] A 12-bit 40 MS/s SAR ADC with Digital Foreground Self-calibration for Capacitor Mismatches |
| Authors |
Injune Yeo;Byung-geun Lee |
| DOI |
https://doi.org/10.5573/JSTS.2020.20.1.105 |
| Keywords |
Successive approximation register; analog-to-digital converter; dynamic comparator; input-referred noise; capacitor mismatch; self-calibration |
| Abstract |
This study presents a 12-bit 40 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a digital foreground self-calibration scheme for capacitor mismatches and a low-noise dynamic comparator. To reduce hardware complexity and AD power consumption, a split-capacitor, capacitive digital-to-analog converter (CDAC) is used to generate the comparator input voltage for binary search operations at the cost of increased capacitor matching requirements. Capacitor mismatches were calibrated with the digital foreground self-calibration technique, which was modified from our previous work to be adapted for the split-capacitor CDAC. In addition, a low-noise dynamic comparator that does not need an additional circuit and conversion cycles is also presented. A prototype ADC, which occupies an active die area of 0.098 mm2, is fabricated with a 65 nm standard CMOS process. By using the mismatch calibration scheme, the ADC achieves a spurious-free dynamic range and a signal-to-noise and distortion ratios of 79.0 dB and 67.4 dB, respectively, for a sampling rate of 40-MSample/s. The power consumption of the ADC is 1.96 mW when driven with a 1.2 V supply and the figure-of-merit is 25.58 fJ/conversion-step. |