This study presents a 12-bit 40 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a digital foreground self-calibration scheme for capacitor mismatches and a low-noise dynamic comparator. To reduce hardware complexity and AD power consumption, a split-capacitor, capacitive digital-to-analog converter (CDAC) is used to generate the comparator input voltage for binary search operations at the cost of increased capacitor matching requirements. Capacitor mismatches were calibrated with the digital foreground self-calibration technique, which was modified from our previous work to be adapted for the split-capacitor CDAC. In addition, a low-noise dynamic comparator that does not need an additional circuit and conversion cycles is also presented. A prototype ADC, which occupies an active die area of 0.098 mm$^{\mathbf{2}}$, is fabricated with a 65 nm standard CMOS process. By using the mismatch calibration scheme, the ADC achieves a spurious-free dynamic range and a signal-to-noise and distortion ratios of 79.0 dB and 67.4 dB, respectively, for a sampling rate of 40-MSample/s. The power consumption of the ADC is 1.96 mW when driven with a 1.2 V supply and the figure-of-merit is 25.58~fJ/conversion-step.

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## I. Introduction

Owing to simple architecture and advance in CMOS technologies, the successive approximation
register (SAR) analog-to-digital converter (ADC) has demonstrated its ability to achieve
high energy-efficiency in various applications ^{(1-}^{4)}. A typical SAR ADC includes a dynamic comparator, capacitive digital-to-analog converter
(CDAC), and SAR logic, which operate to find the nearest digital code to an input
voltage based on the binary search algorithm. These building blocks of SAR ADCs scale
very well with sub-nano technologies as they are less affected by the degraded intrinsic
gain and reduced supply voltage. Despite the architectural advantage, there are two
major limitations in the SAR ADC implementation with fine resolution above 12 bits:
a) capacitor mismatch in the CDAC and b) the thermal noise in the dynamic comparator.
These constraints result in the SAR ADCs having a large size and low bandwidth, which
hinder the enhancement of the overall performance. To address the above challenges,
various techniques have been developed and successfully achieved the desired linearity
and accuracy.

In the capacitor mismatch cases, calibration techniques such as dithering ^{(4)}, noise shaping ^{(5)}, trimming with capacitor banks ^{(6)}, charge compensation ^{(7)}, and ADC transfer function inference using forward-reverse switching ^{(8)} have been proposed to correct the error. However, these techniques perform the calibration
in the analog domain. Hence, they use either additional CDACs ^{(7)}, extra conversion cycles ^{(5,}^{8)}, or comparator offset calibration pre-processing ^{(4,}^{6,}^{8)}, which require an increased die areas and power consumptions. To minimize the design
overhead, calibration techniques in the digital domain have also been reported. For
example, in ^{(9)}, the capacitor mismatch error is minimized using the least-mean-square (LMS) algorithm
based on comparison of the digital output between a main ADC and additional accurate-but-slow
ADC. Instead of using an additional reference ADC, the digital calibration techniques
that utilize the offset perturbation ^{(10)}, missing code ^{(11)}, and DNL/INL histogram ^{(12)} have been proposed. However, excessive hardware for heavy computation is necessary
for these techniques to calculate the capacitor mismatch.

Thermal noise of the dynamic comparator can increase the probability of bit-decision
error and raise the quantization noise floor at the ADC output spectrum. In ^{(13)}, instead of one comparator, low-power coarse and high-power fine comparators are
used to minimize the comparator noise based on the fact that the comparator noise
performance did not need to be always high during the entire span of the conversion
cycles. However, the offset mismatch between the two comparators can degrade the linearity
of the ADC output. A data-driven noise technique utilizing majority voting has been
presented in ^{(14)} and successfully improved the comparator accuracy at the cost of increased conversion
speed. In ^{(15)}, an adaptive averaging technique was introduced based on the use of the last 3 least
significant bits, however, an additional DAC switching was required which increased
hardware complexity.

In this study, simple yet effective capacitor mismatch calibration and dynamic comparator
noise reduction techniques are presented that are free of the aforementioned issues.
The calibration technique, which has been modified from that presented in our previous
study ^{(16)}, allows a foreground self-calibration of the DAC capacitor mismatch, and the proposed
dynamic comparator effectively suppresses thermal noise by using time-domain current
integration without increased hardware complexity and conversion cycles.

To demonstrate the proposed techniques, a prototype of low-power, and small-size 12-bit SAR ADC was fabricated in the 65 nm standard CMOS process. The ADC occupies a die area of 0.098 mm$^{2}$ and dissipates a 1.96mW from a 1.2-V power supply. The measured differential nonlinearity and integral nonlinearity are respectively improved from +2.11/-0.95 and +4.00/-4.08 LSB to +0.97/-0.93 and +1.11/-1.28 LSB by applying the calibration technique. Operating at 40 MS/s, the ADC achieves spurious-free dynamic range (SFDR) and signal-to-noise distortion ratios (SNDRs) of 79.0 dB and 67.d dB, respectively, with applying the mismatch calibration for a near-Nyquist-rate input. This results in a figure-of-merit (FOM) of 25.58 fJ/conversion-step

The rest of this study is organized as follows. Section II and Section III explains the proposed capacitor-mismatch calibration and low input-referred-noise comparator, respectively. Section IV presents the detailed circuit implementation. The prototype SAR ADC measurement results are presented in Section V followed by conclusion in Section VI.

## II. Proposed Capacitor Mismatch Calibration Technique

In our previous study ^{(16)}, we proved based on behavioral simulations that a capacitor mismatch error induced
by a certain capacitor in the CDAC yielded an antisymmetric behavior as the input
amplitude was swept from zero to the full-scale voltage which is normally a reference
voltage (V$_{\mathrm{REF}}$). Therefore, an average value of the mismatch error approaches
to zero when the input amplitude slowly increases from zero to V$_{\mathrm{REF}}$.
Based on this fact and the CDAC capacitor switching scheme presented in ^{(16)}, the amount of capacitor mismatch can be found without modifying the conventional
SAR ADC architecture.

However, the CDAC switching scheme and the mathematical derivation presented in ^{(16)} can be applied only to a binary-weighted CDAC that uses a bottom-plate sampling method
^{(17,}^{18)}. Despite the fact that the binary-weighted DAC architecture is simple and easy to
implement, the number of unit capacitors, and hence the die area grows exponentially
with respect to the ADC resolution. For example, 2048-unit capacitors are needed for
a 12-bit SAR ADC. A more area-efficient implementation is a split-capacitor CDAC [4,
7, 9, 11, 12, 15]. The required unit capacitor number is greatly reduced by placing
a decoupling capacitor, which is often referred to as an attenuation capacitor, between
the MSB and LSB capacitor arrays at the cost of increased requirement for capacitor
matching. The number of unit capacitor for a 12-bit SAR ADC reduces to 96, and is
almost 21 times smaller than that of the binary-weighted CDAC. However, the capacitor
matching requirement increases considerably by the square root of 21.

Fig. 3. Proposed CDAC switching procedure for capacitor mismatch estimation. (a) V$_{\mathrm{REFP}}$ sampling with C$_{\mathrm{i}}$ being connected to V$_{\mathrm{CM}}$, (b) Vin sampling without C$_{\mathrm{i}}$, (c) C$_{\mathrm{i}}$ being connected to V$_{\mathrm{CM}}$ for SAR conversion.

Bottom-plate sampling of the input signal using a CDAC increases the conversion time
and switching energy of a CDAC because an additional clock phase is needed during
which the top-plate of the CDAC settles to the input sample voltage by connecting
all the bottom-plate switches to an AC ground ^{(17)}. To avoid the drawbacks of bottom-plate sampling, a top-plate sampling scheme had
been utilized in previous study ^{(16)}.

In this section, a digital foreground calibration technique is presented, including a new capacitor switching scheme for a split-capacitor array with top-plate sampling and a detailed explanation of its implementation is provided.

### 1. A Split-capacitor CDAC with Top-plate Sampling

Fig. 1 shows a simplified circuit of a conventional SAR ADC employing a split-capacitor CDAC. It consists of the CDAC, dynamic comparator, and SAR control logic. The CDAC is divided into two binary-weighted capacitor arrays, namely, the MSB-capacitor and LSB-capacitor arrays. The MSB and LSB capacitor arrays are used to resolve the M and L-bit, respectively. The attenuation capacitor (C$_{\mathrm{a}}$) can be calculated as follows,

where C$_{\mathrm{u}}$ is the unit capacitor. As shown in Fig. 2, the differential output of CDAC increases or decreases by a specific voltage, which is called a weight in this work, after each bit-cycling is performed. The weights for i-th capacitor in the MSB (i=1, 2, {\ldots}, M) and LSB (i=L, L+1, {\ldots}, M+L+1) arrays, W$_{\mathrm{i,MSB}}$ and W$_{\mathrm{i,LSB}}$, can be respectively represented as follows,

##### (3)

$W_{i, \mathrm{LSB}}=\frac{C_{a}}{C_{a}+C_{M T}} \frac{C_{i}}{C_{L T}+C_{a} \| C_{M}} \frac{V_{R E F}}{2}$where C$_{\mathrm{MT}}$ and C$_{\mathrm{LT}}$ are the total equivalent capacitances of the MSB and LSB capacitor arrays, respectively. C$_{\mathrm{a}}${\textbar}{\textbar}C$_{\mathrm{LT}}$ represents a parallel combination of C$_{\mathrm{a}}$ and C$_{\mathrm{LT}}$ which can be calculated as (C$_{\mathrm{a}}$${\cdot}$C$_{\mathrm{LT}}$)/(C$_{\mathrm{a}}$+C$_{\mathrm{LT}}$). After the last bit decision is made, the reconstructed ADC input signal can be calculated by using the W$_{\mathrm{i,MSB}}$ and W$_{\mathrm{i,LSB}}$ as follows

Fig. 4. Weight estimation procedure for the MSB capacitor (C1). CDAC output voltages with proposed switching (a) and weight estimation using the digitized CDAC outputs (b).

##### (4)

$\begin{aligned} V_{i n}= 2\left(\sum_{i=1}^{M} D_{i} \cdot W_{i, \mathrm{MSB}}+\sum_{i=L}^{M+L} D_{i} \cdot W_{i, L \mathrm{SB}}\right)+\mathrm{D}_{M+L+1} \cdot W_{M+L+1, L S B}+V_{Q} \end{aligned}$where D$_{\mathrm{i}}$ is an i-th bit of the ADC output code, and V$_{\mathrm{Q}}$ is a quantization error.

### 2. Estimation of Capacitor Mismatch

In the presence of capacitor mismatches, the actual weights deviate from the theoretical values as in (2) and (3). The mismatch calibration can be achieved by estimating the actual weights and by applying those to reconstruct the ADC input sample.

The weight associated with the i-th capacitor (C$_{\mathrm{i}}$) in the capacitor array (W$_{\mathrm{i}}$) can be calculated with the use of the proposed CDAC switching scheme as follows.

Firstly, as shown in Fig. 3(a), the positive reference voltage (V$_{\mathrm{REFP}}$) is only sampled on C$_{\mathrm{i}}$ by connecting the top-plate and bottom-plate of C$_{\mathrm{i}}$ to V$_{\mathrm{REFP}}$ and the common-mode voltage (V$_{\mathrm{CM}}$), respectively, and keeping other capacitors floating. Secondly, the ADC input signal (V$_{\mathrm{in}}$) is sampled on all the capacitors except for C$_{\mathrm{i}}$, as shown in Fig. 3(b). Finally, the bottom-plates of all the capacitors are connected to V$_{\mathrm{CM}}$ and the node voltage of the top-plate, which is denoted as V$_{\mathrm{CDAC}}$(2n-1) in Fig. 3(c), becomes

##### (5)

$V_{CDAC}\left(2n-1\right)=\left(\frac{C_{i}}{C_{MT}+\left.C_{a}\right\| C_{LT}}\right)V_{REFP} +\left(\frac{C_{MT}+\left.C_{a}\right\| C_{LT}- C_{i}}{C_{MT}+\left.C_{a}\right\| C_{LT}}\right)V_{in}\left(2n-1\right)$After sampling with weight estimation switching, V$_{\mathrm{CDAC}}$(2n-1) is then converted into a digital binary code.

The above procedure is repeated using the next input sample and the negative reference voltage (V$_{\mathrm{REFN}}$) instead of V$_{\mathrm{REFP}}$. V$_{\mathrm{CDAC}}$(2n) is then calculated as follows

##### (6)

$V_{CDAC}\left(2n\right)=\left(\frac{C_{i}}{C_{MT}+\left.C_{a}\right\| C_{LT}}\right)V_{REFN}\\ +\left(\frac{C_{MT}+\left.C_{a}\right\| C_{LT}- C_{i}}{C_{MT}+\left.C_{a}\right\| C_{LT}}\right)V_{in}\left(2n\right)$The sampling and conversion process used to obtain digital codes for V$_{\mathrm{CDAC}}$(2n-1) and V$_{\mathrm{CDAC}}$(2n) is repeated N times. Then the average values of the digitized V$_{\mathrm{CDAC}}$(2n-1) and V$_{\mathrm{CDAC}}$(2n) are subtracted from each other and a digital estimate of W$_{\mathrm{i}}$, which is denoted as W$_{\mathrm{Di}}$, can be estimated as follows:

##### (7)

$$\frac{1}{N} \sum_{n=1}^{N} \mathrm{Q}\left[V_{C D A C}(2 n-1)\right]-\mathrm{Q}\left[V_{C D A C}(2 n)\right]=$$ $$+\frac{1}{N}\left(\frac{C_{M T}+C_{a} \| C_{L T}-C_{i}}{C_{M T}+C_{a} \| C_{L T}}\right) \underbrace{\left[\sum_{n=1}^{N} V_{i m}(2 n-1)-V_{i n}(2 n)\right]}_{\text {first term } \approx 0}$$ $$\frac{1}{N} \underbrace{\left[\sum_{n=1}^{N} V_{E}(2 n-1)-V_{E}(2 n)\right]}_{\text {second term } \approx 0} + \underbrace{\left[\sum_{n=1}^{N} V_{Q}(2 n-1)-V_{Q}(2 n)\right]}_{\text {third term } \approx 0}$$ $$+\underbrace{\frac{1}{N} \sum_{n=1}^{N}\left(\frac{C_{i}}{C_{M T}+C_{a} \| C_{L T}}\right) V_{R E F} }_{\text {fourth term}}\approx 2 \cdot W_{D i}$$

Fig. 6. Schematic of a conventional dynamic comparator (a), differential output waveform of a comparator during comparison (b), and modification of the input and reset transistors (highlighted in dashed box) for the proposed dynamic comparator (c).

where Q[${\cdot}$] is a quantization operation including decimal conversion. V$_{\mathrm{E}}$ and V$_{\mathrm{Q}}$ are the capacitor mismatch and quantization errors, respectively. Fig. 4 illustrates the weight estimation procedure for the MSB capacitor (C$_{1}$) as a example. With a full-scale sinusoidal input signal, the first term of the right-hand side of (7) approaches zero as N increases. The second and third terms become zero owing to the antisymmetric characteristic of the capacitor mismatch error and random nature of the quantization process, respectively. Fig. 5 shows the simulation (N=256) results for second and fourth term in (7). In this simulation, the capacitor mismatch was assumed to follow a Gaussian distribution with a mean and a standard deviation of 17.94 fF and 0.05 fF, respectively, based on the process data. As shown in Fig. 5, the second and fourth terms approach to zero and the actual weight value (W$_{\mathrm{Di}}$), respectively, as N increases.

## III. Low Noise Dynamic Comparator

A dynamic comparator is extensively used in the implementation of ADCs because it offers a fast decision without dissipating static power. As shown in Fig. 6(a), it is designed with a regenerative circuit which normally consists of back-to-back inverters and a clocked differential pair for sensing the comparator input voltages. Once the comparator starts to trip, the comparator output passes through four different operating regions, namely, reset, sampling, regeneration, and decision, as shown in Fig. 6(b).

The comparator noise is especially important when the comparator input voltage difference
is small enough to place the comparator in a metastable condition in which the voltage
is usually less than one LSB. When the comparator stays in the metastable or near-metastable
conditions, regeneration of the comparator output can be initiated by the comparator
noise. This can increase a probability for the comparator to make an incorrect decision.
In ^{(18)}, it was revealed that the input-referred thermal noise of the comparator can be reduced
by increasing the sampling period. The input-referred noise power of the comparator
can be calculated as follows,

##### (8)

$\sigma_{n, \text {comp}}^{2}=\frac{16 k T \gamma}{3 C_{x}} \cdot \frac{\tau_{s 1}}{t_{\text {sample}}}+\frac{16 k T \gamma}{3 C_{\text {out}}} \cdot \frac{\tau_{s 1}^{2} \tau_{s 2}}{\left(t_{\text {sample}}\right)^{3}}$where k, T, and ${\gamma}$ are respectively the Boltzmann constant, absolute temperature,
and the process dependent excess noise factor. C$_{\mathrm{P}}$ and C$_{\mathrm{X}}$
are the total parasitic capacitance of the drain of the input transistor (denoted
as P) and the output node. Additionally, ${\tau}$$_{\mathrm{S1}}$ and ${\tau}$$_{\mathrm{S3}}$
are time constant at the P and the output nodes, respectively. According to ^{(19)}, the comparator noise can be reduced by increasing t$_{\mathrm{sample}}$.

Fig. 7. Comparison time (a) and input-referred noise, (b) of the conventional and proposed dynamic comparators at various N values.

As shown in Fig. 6(c), the proposed comparator makes t$_{\mathrm{sample}}$ longer by sequentially discharging
the voltage at node P. Fig. 7(a) shows the SPICE simulation results of the comparison time of the comparator for different
numbers of series transistors (N). In this simulation, the N varies from 1 to 5, while
the total transistor size is maintained constantly. The comparison time that the comparator
makes a decision after the comparator clock goes high grows with N. Fig. 7(b) also shows the input-referred noise of the comparator for each N. The comparator
noise was obtained by performing periodic steady-state noise simulation ^{(20)} and by calculating the inverse Gaussian cumulative distribution. As expected, the
input-referred noise decreases with N, and a trade-off exists between the input-referred
noise and the comparison time.

Notice that even though the comparison time increases with N, the total conversion
time for each input sample of an asynchronous SAR ADC does not grows as much. The
main reason is that the series transistors do not affect the comparison time when
the input voltage difference is relatively large. Hence the comparator quickly goes
into the regeneration state. They become effective when the input voltage difference
is less than or comparable to one LSB voltage, and only one or two bit-cycles can
meet this condition during the entire conversion time period ^{(21)}. For example, the number of bit-cycling required for the prototype ADC to achieve
a 12-bit resolution including the redundant bits is 15 and the average conversion
time increases from 220.7 ps to 310.5 ps due to the slow bit-cycling. For this reason,
N was set to four to achieve better noise performance.

## IV. Circuit Design

In this section, circuit implementation of the SAR ADC such as the CDAC architecture, a unit capacitor size, and a low-noise dynamic comparator are presented and the operation of the ADC is also explained.

### 1. Architecture of Split-capacitor Array and Redun-dancy for Capacitor Mismatch Calibration

Three design parameters, die area, noise, and capacitor matching need to be considered to determine the architecture of the split-capacitor CDAC. Accordingly, the resolutions of the MSB and LSB sides of the CDAC, which are denoted by the M-bit and L-bit, respectively. The number of unit capacitors for the MSB and LSB capacitor arrays are 2$^{\mathrm{M-1}}$-1 and 2$^{\mathrm{L}}$-1, respectively, and the ADC resolution becomes (M+L+1) bits.

For a SAR ADC, the die area is mostly taken up by the CDAC, especially the number of unit capacitors and the unit capacitor size. The capacitor size also affects the ADC noise performance and matching property of the capacitor.

Table 1. Number of Unit Capacitor According to the M

Fig. 8. Effective number of bits versus structure of M-bit/L-bit split-capacitor array in a 12-bit SAR ADC.

In the case of the split-capacitor CDAC, as listed in Table 1, the total number of unit capacitors grows exponentially as a function of M. Therefore, M should be kept low to save die area. However, the matching requirement of the capacitor also increases as M and this can degrade the ADC linearity. For the sake of die area, M was set to 6 to achieve a minimum number of unit capacitors for a 12-bit SAR ADC. Accordingly, in this study, the capacitor mismatch error was corrected by the calibration technique. Note that the total number of the CDAC capacitors is 21 times smaller than that of the conventional binary-weighted CDAC. The Monte-Carlo simulation results of a 12-bit SAR ADC employing various split-capacitor CDAC architectures with the same matching property explained in Section II-2 are shown in Fig. 8. The simulation was performed with a full-scale sinusoidal signal and capacitor mismatch was assumed to be, in the worst case (binary-weighted structure), 0.2 % of ${\delta}$C/C. The ENOB for before-calibration was calculated using the capacitor weight, W, but after the calibration, the estimated capacitor weight, W$_{\mathrm{D}}$ obtained from the (7), was used to calculate the ENOB. While the effective number of bits (ENOB) decreases as a function of M in case at which mismatch calibration is not used, it remains almost constant with mismatch calibration. Notice that the mismatch calibration does not only improve the ADC performance, but it also saves a significant amount of die area of SAR ADCs based on the utilization of the split-capacitor CDAC.

The ADC noise is composed of three noise components: a) a thermal noise, which is sampled together with the ADC input signal, b) CDAC noise, and c) comparator noise. When the ADC input signal is sampled on the capacitors in the MSB array, the thermal noise is also sampled and its noise power can be calculated as

where k, T, and C$_{\mathrm{MT}}$ are respectively the Boltzmann constant, absolute temperature, and the total capacitance of the MSB-capacitor array. The LSB-side capacitors are not included in (9) because they are reset to V$_{\mathrm{CM}}$ during the input sampling.

After the input sampling is completed, the SAR conversion starts and the CDAC sequentially
generates the output voltage, which is also the comparator’s input, based on the decision
of the comparator. Starting from the MSB capacitor, the bottom-plate of a capacitor
in the capacitor array is sequentially connected to either V$_{\mathrm{REFP}}$ or
V$_{\mathrm{REFN}}$ depending on the comparator output for each bit-cycling. As shown
in Fig. 9, thermal noise generated from the bottom-plate switch (S$_{\mathrm{i}}$) ^{(15,}^{22)} is also stored on the capacitor during the bit-cycling period and the noise power
at the bottom-plate (BP) of C$_{\mathrm{i}}$ in the MSB or LSB capacitor arrays can
be respectively calculated as

##### (10)

$V_{n,\mathrm{C}_{\mathrm{i},MSB},BP}^{2}=\frac{kT}{\left.C_{i}\right\| \left(C_{MT}- C_{i}+\left.C_{a}\right\| C_{LT}\right)}$

##### (11)

$V_{n,\mathrm{C}_{\mathrm{i},LSB},BP}^{2}=\frac{kT}{\left.C_{i}\right\| \left(C_{LT}- C_{i}+\left.C_{a}\right\| C_{MT}\right)} $Then, the CDAC output noise power, which is the input to the comparator (node Z), can be calculated by applying a capacitive division between C$_{\mathrm{i}}$ and other capacitors as flows:

##### (12)

$V_{n,\mathrm{C}_{\mathrm{i},MSB},\mathrm{Z}}^{2}=V_{n,\mathrm{C}_{\mathrm{i},MSB},BP}^{2}\cdot \left(\frac{C_{i}}{C_{MT}+\left.C_{a}\right\| C_{LT}}\right)^{2}$

##### (13)

$V_{n,\mathrm{C}_{\mathrm{i},LSB},\mathrm{Z}}^{2}=V_{n,\mathrm{C}_{\mathrm{i},LSB},BP}^{2}\cdot \left(\frac{C_{i}}{C_{LT}+\left.C_{a}\right\| C_{MT}}\frac{C_{a}}{C_{MT}+C_{a}}\right)^{2}$

##### (14)

$V_{n,CDAC}^{2}=\sum _{i=1}^{M}V_{n,\mathrm{C}_{\mathrm{i},MSB},\mathrm{Z}}^{2}+\sum _{i=M+1}^{M+L+1}V_{n,\mathrm{C}_{\mathrm{i},LSB},\mathrm{Z}}^{2}$In (13), the sampled thermal noise generated from the LSB capacitors is smaller than the thermal noise generated by the MSB capacitors because it is attenuated due to the capacitive division of CMT and Ca. According to (9) and (14), the total sampled thermal noise can be reduced by increasing CMT or equivalently the number of unit capacitors in the MSB-capacitor array. The total noise power for a differential SAR ADC can be calculated as follow:

Fig. 10. The total ADC noise for various unit capacitance and the percentage of the noise contribution with an 18 fF unit capacitance.

The simulated comparator noise, which will be discussed in the Section III, is 120 ${\mathrm{\mu}}$V$_{\mathrm{RMS}}$. For the selected split-capacitor CDAC architecture, the simulated ADC noise with various unit capacitances are shown in Fig. 10. To meet the target SNDR of 70 dB with a full-scale input amplitude of 1.6-V$_{\mathrm{pp}}$, the total noise power should be set to take values below 178 ${\mathrm{\mu}}$V$_{\mathrm{rms}}$. Therefore, a unit capacitance of 18fF was selected in this study.

Fig. 11 shows a circuit diagram of the 12-bit SAR ADC. The MSB and LSB capacitor arrays,
which consist of 6 and 5 binary-weighted capacitors, resolve 6 and 5-bits, respectively.
The ADC uses 15-bit conversion cycles for an effective 12-bit resolution. Three extra
cycles are used to generate redundant bits due to the following two reasons. First,
capacitor mismatches between the capacitors used in the ADC are measured by the ADC
itself without using extra circuits or capacitors. This process is often called a
self-calibration. If the ADC output has a missing code while the mismatch calibration
is executed, the mismatch information is lost and the mismatch error can be corrected.
The number of redundant bits is determined based on the matching property of the capacitor
given by the process. Second, redundancy also helps to correct the error caused by
incomplete settling of the CDAC output ^{(23)}. By maintaining the same redundancy during normal operations, the DAC settling error
tolerance increases by almost 20 %.

The timing diagram of the ADC is shown in Fig. 12. The ADC is asynchronously controlled by an internal clock which is generated by
the comparator and a SAR logic ^{(24,}^{25)}. The external clock controls only the falling edge of the sample clock. During the
sampling phase, the input signal is sampled on the MSB capacitors by connecting the
top and bottom-plates of the capacitors to the input signal and V$_{\mathrm{CM}}$,
respectively, while all the LSB capacitors are reset to V$_{\mathrm{CM}}$. The top-plate
switch is realized with a bootstrapped switch to maintain low impedance over the entire
input range. The conversion cycle starts and a bit-cycling is repeated 15 times with
the use of the asynchronously generated internal flag clock. The V$_{\mathrm{CM}}$-based
monotonic switching scheme presented in ^{(26)} is adapted for the CDAC switching to reduce a switching energy and die area of the
CDAC. As soon as the last bit-cycling finishes, the sampling clock goes high and the
sampling phase for the next ADC input sample begins.

### 2. Dynamic Comparator

Fig. 13 shows a schematic of the dynamic comparator. It is similar to a conventional dynamic comparator except that the input transistor is split into four series transistors that are individually connected to a supply voltage (V$_{\mathrm{DD}}$) through a switch to reduce the input-referred noise by allowing the input transistors to stay in the saturation state for a longer period of time, as explained in Section III.

The operation of the comparator is as follows. When the comparator clock signal (CLKC) is low, the differential outputs of the comparator, which are denoted as V$_{\mathrm{OP}}$ and V$_{\mathrm{ON}}$, and the drain of the series transistors are rest to V$_{\mathrm{DD}}$. As soon as CLKC goes high, both input transistors start to discharge the output parasitic load until either one of the outputs transistors initiate a regeneration process and makes the comparator’s output to a high state. Once the comparison is completed and the comparator outputs become available, a flag signal is generated by XOR-ing the comparator outputs. The ready signal is used to reset the comparator and initiate the next comparison after a short delay for settling the CDAC output. This process is repeated until the last bit is generated by the comparator.

The transistor sizes, which are listed in Table 2, are determined based on the noise and transient simulations to meet both noise and speed requirements. The simulated input-referred noise was 120 uV$_{\mathrm{RMS}}$.

Fig. 16. Measured dynamic performance before (gray line) and after (black line) calibration with input frequencies of Fin = 1.83 MHz (a) and Fin = 18.7 MHz (b).

## IV. Prototype Design and Measurement Results

The ADC, which occupies an active die area of 0.098mm2, was fabricated with a 65 nm CMOS process. The chip micrograph is shown in Fig. 14. The calibration logic illustrated in Fig. 14 automatically selects the capacitor one by one, when the calibration enable signal is asserted. The calibration logic consists of a frequency divider and shift register and synchronized to the main clock. For each capacitor, 4096 data points are captured by the logic analyzer. After then, calculate the weight through the calibration decoder implanted with off-chip in software.

The ADC performances were measured before and after calibration, and the mismatch calibration was performed with a full-scale sinusoidal signal. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) before and after the calibration are shown in Fig. 15. The measured DNL and INL before calibration are less than +2.11/-0.95 and +4.00/-4.08 LSB, respectively. It is worth noting that the missing code is not occurred (the DNL less than -1.00 LSB) due to the redundancy scheme. After calibration, the DNL and INL improve to +0.97/-0.93 and +1.11/-1.28 LSB, respectively. The measured dynamic performances are shown in Fig. 16. A 32768-points fast Fourier transform was performed by using the ADC output codes captured at a sampling rate of 40-Msample/s. The measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) before calibration are 60.1 and 67.5 dB, respectively, for a full-scale sinusoidal signal with a frequency of 1.83 MHz. After calibration, the SNDR and SFDR improves to 69.3 and 81.2-dB by 9.2 and 13.7-dB, respectively. With a high frequency input signal of 18.7 MHz, the SNDR and SFDR values are 57.2 and 65.2-dB before calibration and 67.4 and 79.0-dB after calibration, respectively. The overall dynamic performance of the ADC is improved by approximately 10.2 dB, and resulted in a 1.4-bit improvement of the effective number of bits (ENOB). Fig. 17 also shows the measured SNDR and SFDR values at various input frequencies. The dynamic performances were well maintained for the input frequencies from DC to near Nyquist rate.

Note that although a low-frequency sinusoidal signal was applied to the ADC as a calibration input signal for measuring the capacitor mismatch, a waveform of the calibration input signal does not affect the calibration results as long as the amplitude of the calibration signal is close to full scale. Fig. 18 shows the measured SNDR and SFDR for various calibration signal amplitudes. The x-axis shown the input amplitude which is normalized to that of a full-scale signal and the y-axis is the dynamic performance measured with a Nyquist rate input signal. As shown in Fig. 18, the measured SNDR and SFDR after calibration increase with an amplitude of the calibration signal. To properly collect mismatch information, all the capacitors in the CDAC should be involved in the CDAC switching and this condition can be met with input signal amplitudes which are close to the full scale.

The total power consumption of the ADC is 1.96 mW for a power supply of 1.2 V. The CDAC, the comparator, and the SAR logic consume 0.26 (13.3%), 0.45 (22.9%), and 1.25-mW (63.8%), respectively. The measured figure-of- merit (FOM), which is defined by

Table 3. Specification Summary

is 25.58 fJ/conversion-step at the Nyquist rate. Where ERBW represents the effective resolution bandwidth. Note that the SAR logic consumes a considerable amount of power which is almost 64% of the total ADC power. This indicates that the power efficiency of the ADC can be improved significantly with a more advanced CMOS process, which generally offers an aggressive transistor scaling for digital logic applications.

The performance of the ADC is summarized in Table 3 and 4 compares the ADC performance with the recently published works ^{(27-}^{29)}. The ADC performance is comparable to that of the state-of-the-art SAR ADCs which
were fabricated in more advanced CMOS processes.

## VI. Conclusion

A 12-bit 40MS/s SAR ADC that utilized a digital foreground self-calibration method for capacitor mismatches and a low-noise dynamic comparator was proposed and fabricated with a 65 nm standard CMOS process. The ADC used a split-capacitor CDAC architecture to reduce the die area and CDAC switching power, and the digital calibration technique presented in our previous work was modified and successfully applied to the split-capacitor CDAC of the ADC. The dynamic comparator reduced the input-referred noise by splitting the input transistor into four transistors connected in series, and by increasing the sampling period of a comparison time. The static performances, especially INL, were improved by using the calibration. The measured DNL and INL before the calibration are less than +2.11/-0.95 and +4.00/-4.08 LSB, respectively. After calibration, the DNL and INL improved to +0.97/-0.93 and +1.11/-1.28 LSB, respectively. The dynamic performances also improved with the calibration. The measured SNDR and SFDR for a low-frequency full-scale sinusoidal inputs after calibration were 69.3 and 81.2 dB, respectively. With a high frequency input signal of 18.7 MHz, the SNDR and SFDR improved to 67.4 and 79.0 dB, respectively, after calibration. The ADC consumes 1.96 mW from a 1.2 V power supply and achieves an ENOB of 10.9-bit at Nyquist rate, which resulted in a FOM of 25.58 fJ/conversion-step.

Table 4. Performance Comparison with Other Related Works

*BW-: Binary Weighted Capacitive DAC / PI-: Pipelined/ SC-: Split Capacitive DAC NS-: Noise Shaping

### ACKNOWLEDGMENTS

This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2018-0-01433) supervised by the IITP (Institute for Information & communications Technology Promotion) and the MOTIE Research Grant of 2020 (10067764).

### REFERENCES

## Author

Injune Yeo received the B.S. degree in Semiconductor Science from Dongguk University, Seoul, Korea, in 2011, and the M.S. degree in mechatronics engineering from Gwangju Institute of Science and technology (GIST), Gwangju, Korea, 2014, where he is currently pursuing the Ph.D. degree.

His current research interests include analog-to-digital converter, and NVM resistive processing element based neural network design.

Mr. Yeo was a co-recipient of the Commissioner of the Korean Intellectual Property Office Award at the 16th Korea Semiconductor Design Contest in 2015 and was a co-recipient of the SK-Hynix Award at the 18th Korea Semiconductor Design Contest in 2017.

Byung-geun Lee (S’04-M’08) received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 2000.

He received the M.S. and the Ph.D. degrees in electrical and computer engineering from the University of Texas at Austin in 2004 and 2007, respectively.

From 2008 to 2010, he was a senior design engineer at Qualcomm Incorporated, San Diego, CA, where he had been involved in the development of various mixed-signal ICs.

Since 2010, he has been with Gwangju Institute of Science and Technology (GIST), and currently he is a professor at the school of electrical engineering and computer science.