Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2020-02 (Vol.20 No.01)
  4. 10.5573/JSTS.2020.20.1.093
XML PDF INFO REF

REFERENCES

1 
Kuo Y., Mar 2008, Thin-film transistor and ultra-large scale integrated circuit: Competition or collaboration, Jpn. J. Appl. Phys., Vol. 47, No. 3, pp. 1845-1852Google Search
2 
Lu H. Y., Chang T. C., Tai Y. H., Liu P. T., Chi S., Dec 2007, A new pixel circuit compensating for brightness variation in large size and high resolution AMOLED displays, J. Display Technol., Vol. 3, No. 4, pp. 398-403Google Search
3 
Ma R. Q., Hewitt R., Rajan K., Silvernail J., Urbanik K., Hack M., Brown J. J., Jan 2008, Flexible active-matrix OLED displays: Challenges and progress, J. Soc. Inf. Display, Vol. 16, No. 1, pp. 169-175DOI
4 
Yu Y. H., Lee Y. J., Li Y. H., Kuo C. H., Li C. H., Hsieh Y. J., Liu C. T., Chen Y. J. E., May 2009, An LTPS TFT demodulator for RFID tags embeddable on panel displays, IEEE Trans. Microw. Theory Tech., Vol. 57, No. 5, pp. 1356-1361DOI
5 
Yamauchi N., Hajjar J.-J. J., Reif and R., Jan 1991, Polysilicon thin film transistors with channel length and width comparable to or smaller than the grain size of the thin film, IEEE Trans. Electron Devices, Vol. 38, No. , pp. 55-60DOI
6 
Kouvatsos D. N., Voutsas A. T., Hatalis and M. K., Sep 1996, High-performance thin-film transistors in largegrain size polysilicon deposited by thermal decomposition of disilane, IEEE Trans. Electron Devices, Vol. 43, No. 9, pp. 1399-1406DOI
7 
Ortiz-Conde J. G. Fossum and A., Aug 1983, Effects of grain boundaries on the channel conductance of SOI MOSFET’s, IEEE Trans. Electron Devices, Vol. 30, No. , pp. 933-940DOI
8 
Dimitriadis C. A., Sept 1997, Grain boundary potential barrier inhomogenities in low-pressure chemical vapor deposited polycrystalline thin film transistors, IEEE Trans. Electron Devices, Vol. 44, No. , pp. 1563-1565DOI
9 
Swartz G. A., 1982, Computer model of amorphous silicon solar cell, J. Appl. Phys., Vol. 53, No. 1, pp. 712-719DOI
10 
Guerrieri R., Ciampolini P., Gnudi A., Rudan M., Baccarani G., Aug 1986 , Numerical simulation of polycry-stalline-silicon MOSFET's, IEEE Trans. Electron Devices, Vol. 33, No. , pp. 1201-1206DOI
11 
Walker P. M., Uno S., Mizuta H., 2005 , Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position, Jpn. J. Appl. Phys., Vol. 44, No. 12, pp. 8322-8328DOI
12 
Chou T.-K. A., Kanicki J., Apr 1999, Two-dimensional numerical simulation of solid-phase-crystallized polysilicon thin-film transistor characteristics, Jpn. J. Appl. Phys., Vol. 38, No. , pp. 2251-2255DOI
13 
Kimura M., Eguchi T., Shimoda S. Inoue and T., Aug 2000, Device Simulation of Grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors, Jpn. J. Appl. Phys., Vol. 39, No. , pp. 775-778DOI
14 
Kimura M., Inoue S., Shimoda T., Jan, Dependence of polycrystalline silicon thin-film transistor charac-teristics on the grain-boundary location, J. Appl. Phys., Vol. 89, No. , pp. 596-600DOI
15 
Wang A. W., Saraswat K. C., May 2000, A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors, IEEE Trans. Electron Devices, Vol. 47, No. 5, pp. 1035-1043DOI
16 
Cheng C. F., Jagar S., Poon M. C., Kok C. W., Chan M., Dec 2004, A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology, IEEE Trans. Electron Devices, Vol. 51, No. 12, pp. 2061-2068DOI
17 
Kitahara Y., Toriyama S., Sano N., Dec 2003, Statistical study of subthreshold characteristics in poly-crystalline silicon thin-film transistors, J. Appl. Phys., Vol. 94, No. 12, pp. 7789-7795DOI
18 
Moon G., Sohn Y., Choi K., Kim Y., Park K., pp 145-151 Jul 2017, Investigation of the drain-induced barrier lowering of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length, Journal of Information Display, Vol. 18, No. , pp. -DOI
19 
Kim S. Y., Baytok S., Roy K., Mar 2011, Scaled LTPS TFTs for low-cost low-power applications, Proc. 12th Int. Symp. Quality Electron. Design, Vol. , No. , pp. 1-6DOI
20 
Shockley W., 835 Sep 1952, Statistics of the Recom-binations of Holes and Electrons, Phys. Rev. 87, Vol. , No. , pp. -DOI
21 
Atlas user’s manual (device simulation software) Silvaco , 2018, http://www. silvaco.com, Inc., Santa Clara, CA, Vol. , No. , pp. -DOI
22 
Yoshiyuki K., Shuichi T., Nobuyuki S., Jun 2003, A new grain boundary model for drift-diffusion device simulations in polycrystalline silicon thin-film transistors, Jpn. J. Appl. Phys. Lett., Vol. 42, No. 6, pp. l634-L636DOI
23 
Hillert M., Mar 1965, On the theory of normal and abnormal grain growthSur la theorie des croissances granulaires normale et anormaleZur theorie des normalen und des anomalen kornwachstums, Acta Metallurgica., Vol. 13, No. issue 3, pp. 227-239DOI