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Title [REGULAR PAPER] A New Method for Defect Prediction of Polycrystalline Silicon TFTs with Realistic Grain Boundary Model
Authors K. H. Kim;J. Y. Lee;Y. G. Yoon;S. K. Kim;H. U. Cho;Y. M. Cho;Y. J. Kim;B. D. Choi
Page pp.93-98
ISSN 1598-1657
Keywords Grain-boundary (GB); grain; trap state density; short channel TFT; polysilicon; threshold voltage; deviation
Abstract We investigate the deviation of threshold voltage (Vth) of p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) using a new GB (grain boundary) model that better reflects reality. And we proposed new method for defect prediction using by this new GB model. The new GB model reflects a gaussian distribution of grain size and GB position. And by introducing a new parameter (β) which represents the defect ratio between GB and grain, the Vth deviation that increases as the channel gets shorter can be matched with the actual measurement results. And we found that the increase in the Vth deviation in the short channel becomes larger as the number of defects increases in GB (as the β increases). And we found that the β is an important physical parameter to explain why the Vth deviation of the short channel is rapidly increased. In this way, using this β value in our GB model, it is possible to predict the relative density of defect states of GB in the poly-Si by monitoring the Vth deviation in short channel TFTs in the process of developing polycrystalline TFTs.