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Grain-boundary (GB), grain, trap state density, short channel TFT, polysilicon, threshold voltage, deviation

I. Introduction

Polycrystalline silicon thin film transistors (poly-Si TFTs) technology is expected to be one of the most promising candidates for such as mobile phone applications, flexible displays because of higher mobility and better reliability as compared with other TFT technologies (1-4). And to improve performance of the device, reduction of the channel length of the poly-Si TFT is actively being studied. The reduction in channel length in poly-Si TFTs is advantageous for high performance switching devices, but in terms of deviations it can be disadvantaged by random GB generation in the channel (5-8). Device simulation of the poly-Si TFT predicts and analyses device characteristics. However, the simulation methodology applicable to poly-Si TFT with GB is still in the development stage (9-15). If the poly-Si TFT channel length is long enough despite the GB in the channel obstructing the current flow, there are hundreds to thousands of grains in the channel, so it is often overlooked in poly-Si simulations considering the average GB effect. But as the channel length becomes shorter, the number of GB in the channel is reduced to a comparable level, which necessitates careful study of the GB characteristics. Recently, the model has been modified to reflect that GB statistically in the channel (16-19). We call this model a poly-Si grain boundary model. But most of the poly-Si GB model use the grain size of the poly-Si TFT channel simply as the same value. And there is no clear rule for where to set the grain boundaries in the channel area. However, changes in the position and potential energy of GBs especially in short channel TFTs may affect basic device characteristics (12-14). In this paper, we propose a more realistic GB model in which the grain size and position of the channel change according to the gaussian distribution. And using our GB model, we propose a new method to deduce the defect state of GB by checking the threshold voltage variation.

Fig. 1. (a) Simulation structure: the average grain size is 0.5 ${\mathrm{\mu}}$m, standard deviation is 0.1 ${\mathrm{\mu}}$m with channel length of 3 ${\mathrm{\mu}}$m and width of 1 ${\mathrm{\mu}}$m: the electric field is locally gathered in the GB in the channel @V$_{\mathrm{GS}}$: -2V, V$_{\mathrm{DS}}$: -5V, (b) Comparison of the measurement and TCAD simulation with ${\beta}$=10 and 1000.


Table 1. Device parameters used in the TCAD simulation


II. Simulation Method

Fig. 1(a) shows an example of the cross-sectional structure of the LTPS TFT used in the simulation. The given grain size is 0.5 ${\mu}$m and the number of GB differs according to gate length. As the channel length is 3 ${\mathrm{\mu}}$m, there are seven GB in the channel region. The electric field is locally gathered in every GB when the channel is opened (V$_{\mathrm{GS}}$: -2 V, V$_{\mathrm{DS}}$: -5 V).

The grain size and position of the channel is inherently variable. Therefore, we propose the following simple statistical variables. The grain size in the poly-Si channel depends on the gaussian distribution considering the inherent variations. According to Hillert theory (23), standard grain size distribution theory, the distribution is skewed (not symmetric about the mean). However, the preferred Gaussian distribution was chosen as the statistical model for GB input values, because it focuses on the change in V$_{\mathrm{th}}$ when grain size and GB location are applied as variables, not the distribution of particle size itself. It is assumed that the average and standard deviation of the grain size are 0.5 ${\mathrm{\mu}}$m and 0.1 ${\mathrm{\mu}}$m, respectively and GBs are randomly generated from 0 to 0.5 ${\mathrm{\mu}}$m at the gate edge of the poly-Si substrate. The GB model was created using the Athena and C-interpreter features provided by Silvaco (21).

We performed the 2-D device simulations (‘Atlas’) of 200ea with our GB model as in Table 1. The channel width of the device was fixed at 1 ${\mu}$m, but the channel lengths were varied from 1.5 to 8 ${\mu}$m. The thicknesses of the gate oxide and poly-Si film were 120 nm and 50 nm, respectively. The p-plus doping concentration in the source and drain region was 1${\times}$10$^{20}$ cm$^{-3}$, and the channel region was also doped as p-type with 5${\times}$10$^{15}$ cm$^{-3}$ dopant concentration. The Shockley-Read-Hall recombination and constant mobility model were used in the simulation. The impact ionization was also taken into consideration (20).

For modeling of the I-V characteristics of the p-channel LTPS TFT, the trap state parameters of the grain and GB of polysilicon are optimized. The trap state density of the poly-Si is given by Eqs. (1-5).

$g(E)=g_{T A}(E)+g_{T D}(E)+g_{G A}(E)+g_{G D}(E)$

$g_{TA}(E)=N_{TA}\exp \left[\frac{E- E_{C}}{W_{TA}}\right]$

$g_{TD}(E)=N_{TD}\exp \left[\frac{E_{v}- E}{W_{TD}}\right]$

$g_{GA}(E)=N_{GA}\exp \left[- \left[\frac{E_{GA}- E}{W_{GA}}\right]^{2}\right] $

$g_{GD}(E)=N_{GD}\exp \left[- \left[\frac{E- EGD}{W_{GD}}\right]^{2}\right] $

Where $g_{TA}(E)$ is the density of the density of the acceptor like tail states in the upper half of the bandgap, $g_{TD}(E)$ is the density of the donor like tail stated in the lower half of the bandgap, $g_{GA}(E)$ and $g_{GD}(E)$ are the densities of the acceptor and donor like deep states, respectively. Detailed equations for trap state density are given in (21).

Fig. 2. Histogram of V$_{\mathrm{th}}$ from device simulations (Atlas) with our GB model.


Fig. 3. Defect states in grain and GBs. Ionized trap density is obtained as the product of defect states and Fermi-Dirac function.


It was necessary to decicde whether the defect levels and defect densities of grain and GB are independent variables, respectively, or choose to treat GB and grain defects as only relatively different amounts (ratios) at the same energy level. We choose the latter for simple modeling, and assume that the amount of grain defects can vary from one tenth of a GB to one thousandth of a GB. G.J. Moon et al. also used comparable defect parameters of grain and GB for I-V characteristics [11-13, 17, 18]. Of course, it can be wrong to determine the number of defect states between GB and grain as a simple ratio value and even the ratio values according to the energy levels will be all different. For now, however, while we cannot measure these defects separately, this ratio value has the advantage of simplifying the model for the V$_{\mathrm{th}}$ deviation analysis and makes it possible to find a very interesting fact in a short channel TFT. The ratio is used as an important parameter physically to determine the deviation of V$_{\mathrm{th}}$ in addition to the grain size and GB position.

Here, we define the ratio of the number of defect states in GB to the number of defects in grains as a value of beta (${\beta}$). The unit of the trap density in grain is eV$^{-1}$ cm$^{-3}$, and that at the GB is eV$^{-1}$ cm$^{-3}$. We set a thin region as GB and the thickness of the thin region is 10 nm. So, it is possible to calculate the ratio directly. If ${\beta}$ is 10, meaning that the GB's defect density is 10 times more than the grain's defect density, then the intrinsic properties of GB and the grain region are very well distinguished. The ${\beta}$ value of 1 means that the trap density in GB and grain exist with same values so that they cannot be physically distinguished (as like a-Si model). Fig. 1(b) shows the measurement results and the I-V characteristics simulated by the TCAD simulation and Table 1. lists the main parameters used in the simulation.

As shown in Fig. 2, the distribution of V$_{\mathrm{th}}$ obtained by the simulations using the GB model fits well to the gaussian distribution represented by the solid line. This suggests that our current GB model reflects a realistic change in grain, and then the variations of device characteristics can be predicted.

The donor like defect states (${\beta}$=10) that were used are shown in Fig. 3. The donor like defects are related to the V$_{\mathrm{th}}$ of the p-type channel. This is because the quantity of defect states determines the probability of capturing holes in the valence band. The amount of hole captured (ionized, D+), is defined by the multiplication of the donor like defect states and Fermi-Dirac function, f(T=300K). When the donor like defect value in GB is 10 times to that of grain (${\beta}$=10), the amount of finally captured holes can be increased 36 times from GB to 1.93${\times}$10$^{16}$ cm$^{-3}$ as compared with 5.38${\times}$10$^{14}$ cm$^{-3}$ in the grain. It should be noted that even though a small ratio difference of 10, the captured holes may become quite large. This is because the E$_{\mathrm{f}}$ level in grain is different from that in GB. And effective DOS value for GB and grain also should be different in every beta varying. Below, we will look at how V$_{\mathrm{th}}$ scattering is affected by adjusting the size of the donor-like states in GB along with the ${\beta}$ value.

Fig. 4. V$_{\mathrm{th}}$ measurement result according to channel length (in a glass).


Fig. 5. V$_{\mathrm{th}}$ deviation tendency due to channel length reduction (measurement vs. simulation result).


III. Results and Discussion

Fig. 4 shows how the V$_{\mathrm{th}}$ per channel length in a glass is distributed. As the channel length becomes shorter, V$_{\mathrm{th}}$ positive shift appears, and deviation of V$_{\mathrm{th}}$ also tends to increase. Positive shift of V$_{\mathrm{th}}$ as channel length decreases is explained by the drain induced barrier lowering (DIBL) phenomenon (18,19). And it is expected that as the channel length becomes shorter, a change of the grain size will have a greater influence on the deviation of V$_{\mathrm{th}}$. Therefore, we performed simulations of each length using the proposed GB model to investigate the channel length dependence of the V$_{\mathrm{th}}$ in the poly-Si TFT.

Fig. 5 shows that the deviation of V$_{\mathrm{th}}$ increases as the channel length, L becomes shorter, and it is shown together with the proposed GB model. The dashed line represents the theoretical prediction from the central-limit theorem and is proportional to L$^{\mathrm{-1/2}}$ (22). The normalized standard deviation ${\sigma}$/{\flq}V$_{\mathrm{th}}${\frq} increased as the L decreases. Since the number of GB, which act as highly resistive regions in the channel, is approximately proportional to the active device area. S(=LW) of poly-Si TFT, the variance of threshold voltage {\flq}V$_{\mathrm{th}}$$^{2}${\frq} is expected to be inversely proportional to S. As a result, ${\sigma}$/{\flq}V$_{\mathrm{th}}${\frq} is inversely proportional to L$^{\mathrm{-1/2}}$ when the device width W is fixed. The simulation result through the GB model has the same tendency as the theoretical prediction. However, unlike the measurement results, our simulation results show a significant difference in the short channel (denoted as ${\delta}$ in Fig. 5). This means that we cannot account for the actual V$_{\mathrm{th}}$ deviation considering only GB location and grain size variation.

We assumed various ratios of defects in grain and GB between 1:10 and 1: 1000 (the ${\beta}$ increased from 10 to 1000). And we found a very interesting fact that the V$_{\mathrm{th}}$ deviation in short channels increases as ${\beta}$ values increase (Fig. 5). The same I-V characteristic, but larger ${\beta}$ values mean greater trap density within GB. As the defect density of GB increased, it was found that the contribution to hole capture substantially related to V$_{\mathrm{th}}$ increased further, and that the shorter the channel length, the larger the V$_{\mathrm{th}}$ spread by GB. This suggests that the ${\beta}$ value, which represents the number of defects in GB, is a very important physical factor in analyzing V$_{\mathrm{th}}$ deviations.

IV. Conclusion

We have modified the commonly used poly-Si GB model to be more realistic and have proposed a new parameter ${\beta}$ that relatively shows the number of defect states in GB. Using this model, it is possible to predict V$_{\mathrm{th }}$deviation in the short channel TFT as defect states in the GB. Vice versa, it is possible to approximate how many defect state exists in the GB by simply comparing the V$_{\mathrm{th}}$ deviation of the short channel TFT. The meaning of ${\beta}$ value become even greater when average and standard deviation of grain size are fixed. In general, measurements such as SEM or AFM provide information on the average size and standard deviation of the GB. And unless the crystallization process of Si changes, the average size and standard deviation of the particles do not change significantly. So, the proposed GB model can reflect the average size and standard deviation of the measured grain, and finally it is possible to predict the V$_{\mathrm{th}}$ deviation in the short channel by adjusting only the value of the beta.

Many industries view the defect states of GB (can be represented by the value of ${\beta}$) as a key parameter in the LTPS-backplane (BP) of OLED displays and have spent considerable time and effort to observe them. However, our new method with realistic GB model can significantly reduce time and effort and contribute to product development.


This work was supported by Industrial Human Resources and Skill Development Program (N0001415, Display Expert Training Project for Advanced Display equipments and components engineer) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea). Also, this work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1051493).


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Ki-Hwan Kim

Ki-Hwan Kim received the B.S., M.S. degrees in the Department of Physics from Korea University, Seoul, south Korea, in 2004, and 2006, respectively.

He is currently Ph.D. candidate with the School of Information and Communication Engineering in Sungkyunkwan University, Suwon, south Korea.

In 2006, he joined at Hynics(now, SK-hynics) and In 2011, he joined at Samsung Display Company where he has been working in the area of computer aided engineering.

His interests are TCAD analysis and reliability of Oxide TFT, LTPS for Display.

Soon-Kon Kim

Soon-Kon Kim received the B.S., M.S. degrees in the Department of Information and Communication Engineering, Sungkyunkwan Univer-sity, Suwon, South Korea., in 2013, and 2015, respectively.

He is currently Ph.D. candidate in Sungkyunkwan University, Suwon, south Korea.

His current research interests include display devices

Byoungdeog Choi

Byoungdeog Choi received the Ph.D. degree in electrical engineering from Arizona State University, Tempe, AZ, USA, in 2002.

He is currently a Professor with the School of Information and Communication Engineering, Sungkyunkwan Univer-sity, Suwon, South Korea.

He has authored over 100 articles in SCI journals and holds 50 patents.

His current research interests include display devices and C-MOS technology.