An Ultra-Fast 460-mA Capacitorless DLDO Achieving 8-ns Recovery Time and 99.58% Current
Efficiency
WahlaIbrar Ali1
AkramMuhammad Abrar1
HwangIn-Chul1
-
(Department of Electrical and Electronics Engineering, Kangwon National University,
Chuncheon, Korea)
-
(Qatar University, Doha, Qatar)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Capacitorless, low-dropout regulator, PI controllers, fast transient response.
I. INTRODUCTION
Low-dropout regulators (LDOs) have been extensively utilized as secondary regulators
(after switching-mode converters) in system-on-chip (SoC) devices for efficient and
fast-responsive point-of-load (PoL) power delivery and power management [1]. As shown in Fig. 1, multiple LDOs can be integrated into an SoC without bulky passive components like
inductors and capacitors in switching-mode converters [2]. However, typical LDOs whether analog [3,4,5,6] or digital [7,8,9,10], require a large output capacitor (C${}_{O}$${}_{UT}$) to acquire good load transient
performance by compensating the voltage peaks (undershoot and overshoot) during load
current (I${}_{\rm LOAD}$) switching. When multiple LDOs are required to be integrated
in an SoC to provide PoL power supplies, required number of pad pins and board area
should be proportionally increased in case of external output capacitors (C${}_{O(EXT)}$)
[3,4,5,6,7,8,9,10], as shown in Fig. 1. It may adversely affect the bill-of-material. Alternatively, integrated output capacitors
(C${}_{O(}$${}_{INT}$${}_{)}$) for multiple LDOs aggressively affect the silicon area
which is even more expensive [11,12,13,14]. Therefore, fully-integrated output-capacitorless (OCL) LDOs are highly desirable
for the PoL power delivery and power management in SoC devices [15,16,17,18].
Fig. 1. Simplified block diagram of power delivery network of a SoC.
Several analog LDOs [4,13,19] significantly downscaled the C${}_{O}$${}_{UT}$ to integrate it, however, the silicon
area for this passive component is still used. Also, performances of analog LDOs severely
suffer in low supply voltage. Therefore, the design trends have been shifted from
analog to digital. Compared to analog LDOs, digital LDOs (DLDOs) have better low-voltage
operation, better process scalability, application-specific performance capabilities,
and fewer stability issues.
Fig. 2. Typical SRs based DLDO (a) circuit diagram, (b) load transient response with
and without using C${}_{\rm OUT}$.
(a)
(b)
However, typical DLDOs [8,10,20] still suffer from a fundamental trade-off: the power-speed tradeoff, which mainly
comes from the use of a sampling clock (F${}_{\rm CLK}$) in synchronized comparator
and digital loop controller. Such a typical DLDO is shown in Fig. 2(a) which consists of a clocked comparator, bi-directional shift registers (SRs) and
a PMOS transistor array. This typical SRs DLDO [20] suffers from power-speed tradeoff and it requires a large C${}_{O}$${}_{UT}$ to compensate
for voltage undershoot during I${}_{\rm LOAD}$ variations. Fig. 2(b) illustrates the load transient response of typical SRs DLDO with and without using
C${}_{\rm OUT}$. As shown, for the same I${}_{\rm LOAD}$ step, when the C${}_{\rm
OUT}$ is used, the undershoot ($\Delta$V${}_{\rm REG}$) of the DLDO is much reduced
as compared to the one without C${}_{\rm OUT}$. It is because, upon I${}_{\rm LOAD}$
step, the C${}_{\rm OUT}$ immediately discharges its stored current (I${}_{\rm CAP}$)
to the I${}_{\rm LOAD}$ which compensates for the $\Delta$V${}_{\rm REG}$, even before
the feedback loop starts its operation. However, in the absence of C${}_{\rm OUT}$,
$\Delta$V${}_{\rm REG}$ is quite large as shown in the bottom inset of Fig. 2(b), it is because the feedback loop takes longer time to start responding to the change
in I${}_{\rm LOAD}$. Therefore, to successfully eliminate the C${}_{\rm OUT}$, the
feedback loops response time (T${}_{RES}$) of the DLDO should be very fast to immediately
respond to the I${}_{\rm LOAD}$ for $\Delta$V${}_{\rm REG}$ compensation.
Several DLDOs have been proposed either to downscale the C${}_{\rm OUT}$ [13,14] or to completely remove it [16,17]. However, the significant silicon area is consumed because of on-chip capacitor integration
in [13,14] and the undershoot peaks ($\Delta$V${}_{\rm REG}$) are quite large in [16,17], i.e., 100 mV for 30 mA of $\Delta$I${}_{LOAD.\ }$Also, the I${}_{\rm LOAD}$ driving
capacity of these DLDOs [13,14,16,17] is limited. One of our previously proposed capacitorless DLDO [21] successfully eliminated the need of C${}_{\rm OUT}$ while driving a max I${}_{\rm
LOAD}$ of 235 mA. However, it suffers from a massive $\Delta$V${}_{\rm REG}$ of 200
mV at 235 mA I${}_{\rm LOAD}$ step, which is highly undesirable when the DLDO is supplying
a near-threshold voltage. Such a large $\Delta$V${}_{\rm REG}$ may reset the target
device.
To address these shortcomings, we propose a parallel proportional and integral (PI)
controller based dual-loop capacitorless DLDO. The PI controller is implemented with
the self-shifting bi-directional shift registers (SS-SRs) proposed in [21] together with complimentary connections of PMOS and NMOS power transistors in coarse
switch array. The proposed capacitorless DLDO successfully eliminate the need of a
C${}_{\rm OUT}$ and achieves minimum $\Delta$V${}_{\rm REG}$ while driving wide range
I${}_{\rm LOAD}$. Rest of the paper is organized as follows: Section II shows the
undershoot mitigation technique and detailed architecture of the proposed capacitorless
DLDO including circuit description. Post-layout simulation results are presented in
Section III. Finally, we conclude our paper in Section IV.
II. PROPOSED CAPACITORLESS DLDO
1. Undershoot Voltage Suppression
The simplified block diagram of the undershoot suppression technique in the proposed
capacitorless DLDO is shown in Fig. 3(a). It comprises of the level-triggered clock-less comparators, coarse-loop self-shifting
bidirectional shift registers (SS-SRs) and a switch array which consists of both PMOS
and NMOS power transistors arranged in a complimentary manner. As compared to the
typical DLDOs where only PMOS arrays are used, the NMOS power transistors along with
the PMOS ones form a level-triggered inverter which acts like a typical proportional
(P-control) in addition to the parallel integral (I-control), as shown in Fig. 3(a). The P-control starts its operation at a fixed output point in-contrast to typical
I-control which only starts its operation from zero-state, as illustrated in Fig. 3(b). This results in fast response and shortest latency. In addition, the inverter formed
at power stage operates like strong push-pull device by sourcing the current (from
PMOS power transistors) and sinking the current (through NMOs power transistors),
simultaneously, which results in an immediate current flow to I${}_{\rm LOAD}$ reducing
the overall $\Delta$V${}_{\rm REG}$. Fig. 3(c) shows the simulated load transient response of the proposed capacitorless DLDO. As
shown, when I${}_{\rm LOAD}$ switches from minimum to maximum, an immediate current
(I${}_{PMOS}$+I${}_{NMOS}$) is provided to the I${}_{\rm LOAD}$ to suppress the $\Delta$V${}_{\rm
REG}$.
Fig. 3. (a) Simplified block diagram of the proposed capacitorless DLDO, (b) illustration
of the difference between proposed control and typical control technique, and (c)
simulated load transient response.
(a)
(b)
(c)
2. Detailed Architecture
Fig. 4 shows the detailed block diagram of the proposed capacitorless DLDO. It includes
a level-triggered clock-less stage, a digital controller, which employs a dual-loop
architecture incorporating both coarse- and fine-loop controllers, consists of 64-bit
and 32-bit self-shifting SRs (SS-SRs), finally, the power transistors are also divided
into two groups of coarse and fine switch arrays. The level-triggered clockless stage
is the quantization stage which consists of a logic-threshold-triggered comparator
(LTTC) [21], LTTC-based lock range detector, and a lock synching technique. The clockless LTTC,
operating based on the logic threshold voltage (V${}_{LTH}$) of an inverter, toggles
the 1-bit UD upon detecting V${}_{\rm REG}$. The UD signal indicates ``HI'' if V${}_{\rm
REG}$ is less than V${}_{REF}$, and ``LOW'' if V${}_{\rm REG}$ exceeds V${}_{REF}$.
These conditions dictate the direction of the shift for the coarse-loop output SW${}_{C}$[63:0],
with ``HI'' prompting a right shift and ``LOW'' prompting a left shift. Following
certain feedback loop operations, when SW${}_{C}$[63:0] stabilizes at a target value
where V${}_{\rm REG}$ is approximately equal to V${}_{REF}$, the proposed lock range
detector sets the ``Lock'' signal to high. This action activates the fine-loop SS-SRs
SW${}_{F}$[31:0] and locks the coarse loop, thereby significantly reducing the quiescent
current (I${}_{Q}$) and minimizing steady-state voltage ripples (V${}_{\rm RIPP}$).
The timing diagram of the proposed capacitorless DLDO is shown in Fig. 5. As shown, with the Lock signal, the coarse-fine loop controllers are switched as
follows: coarse loop for Lock = 0 and fine loop for Lock = 1, and these loops are
enabled during startup, load transient state, and steady state, respectively, as shown
in Fig. 5.
Fig. 4. Detailed block diagram of the proposed capacitorless DLDO.
Fig. 5. Timing diagram of the proposed capacitorless DLDO.
3. Lock Range Detector
Fig. 6(a) shows the schematic of the proposed lock range detector. Lock range detector selectively
activates the coarse or fine loop, so that fast transient response time (T${}_{\rm
REC}$) can be acquired while maintaining low levels of V${}_{\rm RIPP}$ and I${}_{Q}$.
As shown, the lock range detector uses a variation of LTTC to obtain the skewed threshold
voltage, by tweaking the size ratio between PMOS and NMOS from the reference ratio
of W${}_{p}$/W${}_{n}$. The working principle and design consideration of the lock
range detector have been explained in detail in [21]. However, the lock range detector with fixed tweaked sizes result in only one fixed
voltage range of V${}_{\rm REG}$ around V${}_{REF}$ which may be changed during the
PVT variation adversely affecting the loop switching of the proposed DLDO. To address
this issue, we propose tuning bits in the lock range detector as shown in Fig. 6(a). The lock range tuning T${}_{1}$[2:0] and T${}_{2}$[2:0] are inserted with toggle
switches at both PMOS side and NMOS to extend the lock range. The extension of lock
range provides the reconfigurability of range which ensures the switching of coarse
loop to fine loop. Furthermore, to ensure that V${}_{\rm REG}$ is always acquired
first before switching the loop from coarse to fine, we delayed the L${}_{RNG}$ by
the four clock cycles of UD with the divider-by-4 circuit clocked by UD, as shown
in Fig. 6(b). The toggling of UD starts when V${}_{\rm REG}$ is sufficiently close to V${}_{\rm
REF}$, otherwise, UD is kept at ``0'' or ``1.'' Therefore, in the case of load transient
regulation, as in Fig. 6(c), the UD stops toggling during peaking, and begins toggling again when V${}_{\rm REG}$
returns to V${}_{\rm REF}$. The designed lock delay resets Lock at the falling edge
of L${}_{\rm RNG}$ and sets Lock again to ``HIGH'' after four cycles of UD. This lock
range detection ensures smooth and accurate loop switching which helps achieving efficient
load regulation.
Fig. 6. (a) Circuit schematic of lock range detector, (b) circuit schematic of lock
synching, and (c) operational waveforms of loop locking.
(a)
(b)
(c)
III. VALIDATION RESULTS
The proposed capacitorless DLDO was designed and fabricated in a 65-nm standard CMOS
process with an overall active area of 0.08 mm${}^{2}$. Fig. 7 shows the die micrograph and layout. The proposed DLDO was designed to supply the
regulated voltage (V${}_{\rm REG}$) in the range of 0.66 V to 1.16V from the V${}_{\rm
DD}$ of 0.7 V to 1.2 V. The proposed DLDO consumes an I${}_{\rm Q}$ of 1.95 mA while
driving a maximum I${}_{\rm LOAD}$ of 460 mA without the need of a C${}_{\rm OUT}$.
Hence, it achieves a peak current efficiency of 99.58% at a max I${}_{\rm LOAD}$ of
460 mA.
Fig. 8 shows the load transient response comparison of the proposed capacitorless DLDO with
our previously proposed capacitorless self-clocked DLDO [21] for an I${}_{LOAD}$ step of 250 mA with a sharp rising edge time (T${}_{EDGE}$) of
1 ns. As shown, the self-clocked DLDO [21] suffers from a massive $\Delta$V${}_{\rm REG}$ of 400 mV which is recovered within
25 ns of T${}_{\rm REC}$. In contrast, the PI controller in the proposed DLDO using
NMOS power transistors significantly reduced this $\Delta$V${}_{\rm REG}$ from 400
mV to only 40 mV for the same I${}_{\rm LOAD}$ step and recovered it within T${}_{\rm
REC}$ of 5 ns. With this, the proposed DLDO reduced the $\Delta$V${}_{\rm REG}$ by
90% and T${}_{\rm REC}$ by 80% as compared to [21]. The proposed DLDO exhibits 23 ns slower start-up response as compared to [21], it is because of the initial current sinking in NMOS power transistors.
Fig. 7. Die micrograph and layout.
Fig. 8. Load transient comparison of the proposed capacitorless DLDO with our previously
proposed self-clocked DLDO [21].
Fig. 9. Simulated load transient response of the proposed capacitorless DLDO at V${}_{\rm
DD} = 1.2$ V, V${}_{REF} =1.16$ V, for a $\Delta$I${}_{\rm LOAD} = 460$ mA changing
at T${}_{EDGE} = 1$ ns.
Fig. 10. Simulated line transient response of the proposed capacitor-less DLDO at
I${}_{\rm LOAD}$ = 0.5 mA.
Fig. 9 shows the simulated load transient response of the proposed DLDO for a load current
step $\Delta$I${}_{\rm LOAD}$ of 460 mA (0 mA-460 mA) with a T${}_{EDGE}$ = 1ns while
supplying V${}_{\rm REG}$ of 1.15 V from V${}_{\rm DD} = 1.2$ V. As shown, the proposed
DLDO exhibits a peak $\Delta$V${}_{\rm REG}$ (undershoot) of 74 mV and overshoot of
50 mV when the I${}_{LOAD\ }$is changed from 0 mA to 460 mA and vice versa. The proposed
DLDO recovers these voltage peaks within 8 ns and 5ns of T${}_{\rm REC}$, as shown
in Fig. 9. Once, the voltage peaks are recovered, the proposed DLDO enters in lock-synching
stage implemented with lock range detector before switching the loop from coarse to
fine. Once, the DLDO enters in steady-state, the V${}_{\rm RIPP}$ are significantly
reduced. The proposed capacitorless DLDO exhibits $< 10$ mV of V${}_{\rm RIPP}$ at
minimum I${}_{\rm LOAD}$.
Fig. 10 shows the simulated line transient response of the proposed capacitor-less DLDO when
V${}_{\rm DD}$ is varied from 1.2 V to 1.15 V ($\Delta$V${}_{\rm DD} = 50$ mV) while
driving a minimum I${}_{\rm LOAD}$ of 0.5 mA. In response to the V${}_{\rm DD}$ variations,
V${}_{\rm REG}$ changes only for $\mathrm{\approx}$ 0.5 mV), as shown in Fig. 10, which results in an overall line regulation of 10 mV/V.
The performance summary of the proposed capacitorless DLDO and its comparison with
the existing state-of-the-art DLDOs are shown in Table I. When compared with [8,9,16,21], the proposed DLDOs exhibits maximum I${}_{\rm LOAD}$ driving capability with minimum
$\Delta$V${}_{\rm REG}$ and T${}_{\rm REC}$ without requiring a C${}_{\rm OUT}$. The
I${}_{\rm Q}$ of the proposed DLDO is slightly higher than [8,16,21]. It is because of the faster self-shifting clock generated by SS-SRs, and because
of the NMOS power transistors which remained turned-on during the steady-state of
the DLDO sinking the current. Even though, the I${}_{\rm Q}$ of the proposed DLDO
is bit higher than [8,16,21] but still the peak current efficiency (Eq. 1) is better than [8] and almost same with [16]. Also, we compared the power efficiency (eq. 2) of the proposed capacitor-less DLDO,
which is significantly better than state-of-the-art DLDOs.
To further evaluate the performance of the proposed capacitor-less DLDO, we compared
the proposed DLDO with state-of-the-art DLDOs on basis of well-known figure-of-merit
(FOM) [1,16,21], given as follows:
As shown, in Table 1, the proposed capacitor-less DLDO outperforms the state-of-the-art DLDOs by achieving
minimum FOM.
Table 1. Performance summary and comparison with the state-of-the-art DLDOs.
|
Parameters
|
This Work
|
[8]
|
[9]
|
[16]
|
[21]
|
|
Process [nm]
|
65
|
65
|
130
|
65
|
65
|
|
Area [mm2]
|
0.08
|
0.059
|
0.18
|
0.075
|
0.069
|
|
Validation
|
Simulated
|
Measured
|
Measured
|
Measured
|
Measured
|
|
COUT [nF]
|
Cap-free
|
0.2
|
1.5
|
Cap-free
|
Cap-free
|
|
VDD [V]
|
0.7 - 1.2
|
0.9 - 1.2
|
0.5 - 1.22
|
0.6 - 1.2
|
0.7 - 1.2
|
|
VREG [V]
|
0.66 - 1.16
|
0.2 - 1.1
|
0.35 - 1.17
|
0.55 - 1.15
|
0.66 - 1.16
|
|
ILOAD, MAX [mA]
|
460
|
19
|
145
|
26
|
235
|
|
ΔVREG [mV] @ ΔILOAD [mA]
|
74 @ 460
|
80 @ 3
|
280 @ 40
|
140 @ 26
|
96 @ 89
|
|
ΔILOAD TEDGE [ns]
|
1
|
5
|
0.1
|
20
|
20
|
|
TREC [ns] @ ΔVREG [mV]
|
8 @ 74
|
90 @ 80
|
55 @ 280
|
95 @ 140
|
77 @ 96
|
|
IQ [µA]
|
1950
|
131
|
3200
|
102 - 167
|
162 - 874
|
|
Peak Current Efficiency [%]
|
99.58
|
99.3
|
97.8
|
99.6
|
99.86
|
|
Peak Power Efficiency [%]
|
95.42
|
91.03
|
93.8
|
92.35
|
94.16
|
|
FOM [ps]
|
0.0013*
|
342
|
63.9
|
0.021
|
0.0013
|
|
Load Regulation [mV/mA]
|
0.004
|
0.15
|
N/A
|
0.04
|
0.2
|
${}^{*}$ In this work, C${}_{\rm OUT} = 0$. Therefore, the parasitic capacitances
of approximately equal to 2 pF of the switch arrays is estimated for FOM calculation.
ACKNOWLEDGMENTS
This research was supported by Basic Science Research Program through the~National
Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2020R1I1A3073683.
The EDA tool was supported by the~IC Design Education Center (IDEC), Korea.
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Ibrar Ali Wahla received his B.E. degree in electronics engineering from the Pakistan
Air-Force Karachi Institute of Engineering and Technology (PAF-KIET), Karachi, Pakistan,
in 2016, and an M.S. degree in electronics engineering from Hallym University, Chuncheon,
Korea, in 2021. He is currently pursuing a Ph.D. in electrical and medical convergent
engineering at Kangwon National University, Korea, commenced in 2021. His research
interests include analog and mixed-signal CMOS integrated circuits, embedded systems,
digital integrated circuit design, and power management. His work has primarily focused
on developing advanced solutions for efficient energy utilization and miniaturization
of circuitry in Power management.
Muhammad Abrar Akram received his B.S. degree in electrical engineering from the
University of Punjab, Lahore, Pakistan, in 2013, and combined M.S. and Ph.D. degree
in Electrical and Medical Convergent Engineering from the Kangwon National University,
Chuncheon, Korea, in 2019. From 2019 to 2023, he was a Post-Doctoral Associate with
the Engineering Division, New York University Abu Dhabi, Abu Dhabi, UAE, where he
extensively worked on the sensing-interface circuits. In 2024, Dr. Akram joined the
Department of Electrical Engineering, Qatar University, Doha, Qatar in 2024, as an
Assistant Professor. His research interests include analog/mixed-signal CMOS integrated
circuits for power management in system-on-chip devices, wireless-powered mm-scaled
biomedical implants, and sensing interface circuits. Dr. Akram received the President
Award and Company Special Award from Korean Semiconductor Industry Association (KSIA),
Korea in 2016 and 2018, respectively. He is the recipient of Best Paper Award at International
Conference on Electronics, Information, and Communication (ICEIC) in 2021.
In-Chul Hwang received his B.S., M.S., and Ph.D. degrees from Korea University,
Seoul, Korea, in 1993, 1995, and 2000, respectively. He was a Post-Doctoral Associate
with the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign,
Urbana, IL, USA, from 2000 to 2001. In 2001, he joined Samsung Electronics, System
LSI Division, Kiheung, Korea, where he led a design team for developing CMOS Global
System for Mobile Communication (GSM)/ Enhanced Data for GSM Evolution/Wideband Code
Division Multiple Access RF transceiver. Since 2007, he has been with the Department
of Electrical and Electronics Engineering, Kangwon National University, Chuncheon,
Korea, where he is currently a Professor. He was a Visiting Scholar with the Georgia
Institute of Technology, Atlanta, GA, USA, in 2012. His current research interests
include digital phase-locked loops for radio-frequency integrated circuits and power
management circuits for dynamic-voltage and frequency scaling applications. Dr. Hwang
was a recipient of the LG Design Contest Grand Prize in 1999 and the DAC Student Design
Contest Award in 2002.