I. Introduction

Due to the rapid development of the Information era, there has been an explosive increase in data demand, leading to the transition from 2D planar to 3D vertical structures in NAND Flash Memory, which is being utilized in various applications ^[1]. Therefore, stacking multiple layers of NAND Flash Memory is necessary to enhance product performance and reduce costs. In future development directions, reducing the cell pitch is inevitable to increase storage density ^[1-3]. However, this reduction in cell pitch leads to a non-ideal effect known as Z-interference. This phenomenon occurs when programming the attack cell causes a change in the threshold voltage (V$_{\mathrm{th}}$) of the victim cell, resulting in decreased cell distribution margin and degraded reliability during program-read operations ^[4].

The main cause of Z-interference is the decrease in electron density in the Poly-Si channel of the victim cell region due to the electrons programmed into the attack cell. To compensate for this decrease in electron density, a higher V$_{\mathrm{read}}$ (read voltage) must be applied to the victim cell, leading to an increase in V$_{\mathrm{th}}$ ^[5]. Various research efforts have been conducted to address this issue, including changes in read operation conditions and program operation conditions. Previous research focused on read operation conditions aimed to minimize V$_{\mathrm{th}}$ variation by altering V$_{\mathrm{read}}$ on the adjacent Word Line (WL) of the attack cell during read operations following programming ^[6]. However, increasing V$_{\mathrm{read}}$ on the WL adjacent to the attack cell can lead to read disturbance due to the movement of electrons within the cell via soft programming during repeated read operations.

Therefore, rather than focusing on changes in read operation conditions, methods focusing on program operation conditions have been proposed. Among these, research aimed at improving Z-interference according to the direction of program operation suggests a Top to Bottom (T-B) operation method rather than the conventional Bottom to Top (B-T) method ^[7]. However, the proposed method may degrade the efficiency of pre-charge operations in the BL direction depending on the program sequence, potentially worsening program disturbance, necessitating meticulous research for multi-level cell operation ^[8].

Another approach in research involves altering the pass voltage of adjacent WLs during program operations. This method utilizes lowering V$_{\mathrm{pass}}$ (pass voltage) of victim cells adjacent to the attack cell ^[9]. However, due to a decrease in the V$_{\mathrm{pass}}$ of adjacent cells, the down-coupling effect reduces the boosting efficiency and causes program disturbance. Therefore, in this paper, we propose a method utilizing asymmetric program-pass voltages to improve both Z-interference and program disturbance, utilizing TCAD simulations.

II. Experiment

Fig. 1(a) compares the conventional program operation method with the proposed program operation method. In the conventional condition, a V$_{\mathrm{pass}}$ of 7 V was applied to the WL adjacent to the victim cell, WL$_{\mathrm{n}}$ ^[9].

In the proposed condition, asymmetric V$_{\mathrm{pass}}$ was applied to the WLs adjacent to WL$_{\mathrm{n}}$. Specifically, a V$_{\mathrm{pass}}$ of 5 V was applied to the WL (WL$_{\mathrm{n-1}}$) in the Source-line (SL) direction, and a V$_{\mathrm{pass}}$ of 9 V was applied to the WL (WL$_{\mathrm{n+1}}$) in the Bit-line (BL) direction ^[10]. The program direction was adopted from Bottom WL to Top WL, following the (B-T) method ^[8]. Therefore, a higher pass voltage was applied to WL$_{\mathrm{n+1}}$, while a lower pass voltage was applied to WL$_{\mathrm{n-1}}$. Additionally, for comparative analysis with previous research, an additional condition was added, wherein a lower pass voltage of 6 V was applied to the WLs (both WL$_{\mathrm{n+1}}$ and WL$_{\mathrm{n-1}}$) adjacent to WL$_{\mathrm{n}}$.

Fig. 1(b) illustrates the NAND Flash structure implemented with a three-dimensional structure and the timing of program operation according to three different pass voltage conditions.

Through TCAD simulation, it was demonstrated that there are five main cells, with three dummy cells on each side to prevent a sharp increase in Bias. Next to them, Source-Select-Line (SSL)/ Drain-Select-Line (DSL) exists to selectively connect cell strings to Common-Source-Line (CSL)/ Bit-Line (BL). The gate length is 25 nm, space length is 20 nm, and channel thickness is 7 nm. The Blocking oxide/ Nitride/ Tunneling oxide layers are set to 6.8 nm/ 4.8 nm/ 5 nm, respectively. The doping concentration of the Polysilicon channel is 1${\times}$10$^{17}$cm$^{-3}$, and the doping concentration of source/drain is 1${\times}$10$^{19}$cm$^{-3}$. The 3D NAND Flash structure, implemented using a cylindrical function to represent the three-dimensional structure, depicts the program operation timing according to the three pass voltage conditions. Additionally, for program operation, BL was set to Ground (0 V), and V$_{\mathrm{core}}$ (approximately 1.8 V) was applied to DSL. Conversely, under program inhibit operation conditions for channel boosting, V$_{\mathrm{core}}$ was applied to BL, and while DSL was set to Ground. The program operation sequence progresses from Common-Source-Line (CSL) to BL. Through this analysis, we investigated the Z-interference characteristics by evaluating the impact on electron trap charge density and channel electron density between cells under different pass voltage conditions. Additionally, we assessed the degree of program disturbance by examining the channel potential of the attacking cell under identical pass voltage conditions during the program inhibit operation ^[9,11,12].

Fig. 1. (a) Conventional program operation and proposed program operation; (b) 3D NAND Flash structure and timing conditions for program operation.

III. Result and Discussions

Fig. 2(a) quantifies the variation in V$_{\mathrm{th}}$ as previously mentioned, illustrating the amount of V$_{\mathrm{th}}$ shift of the victim cell according to the change in V$_{\mathrm{th}}$ when the attack cell is programmed using Incremental Step Program Pulse (ISPP) for various states such as Erase state (E), Program State1 (P1), Program State2 (P2), and so forth ^[13]. The ISPP method was employed, incrementally applying program bias (V$_{\mathrm{pgm}}$) of ${\Delta}$1 V to WL$_{\mathrm{n}}$ ranging from 13 V to 20 V. Simulating the scenario where the attack cell (WL$_{\mathrm{n}}$) V$_{\mathrm{th}}$ increases from approximately -3 V to 5 V to mimic program states such as P1, P2, P3, and P7 and the corresponding change in victim cell (WL$_{\mathrm{n-1}}$) V$_{\mathrm{th}}$ was observed. The measurement results indicate that under the 5/9 V pass voltage condition, the victim cell's V$_{\mathrm{th}}$ shift is the lowest. Fig. 2(b) show the profile of charge trapped in the charge trap nitride (CTN) at the attack cell area and the influence of electric-field under three pass voltage conditions, respectively [9, 14-16]. It is evident that when trapped charge is programmed in the attack cell area, it is closest to the victim cell under the 7/7 V pass voltage condition, followed by the 6/6 V condition, and farthest under the 5/9 V condition. A higher number of electrons trapped in the attack cell's CTN implies a greater impact on the variation of the victim cell's V$_{\mathrm{th}}$. Changing the pass voltage condition from 7/7 V to 6/6 V reduces Z-interference by reducing the number of trapped electrons between the attack cell and the victim cell, thereby lowering the electric field’s influence on the Poly-Si channel beneath the victim cell. Conversely, applying a pass voltage of 9 V to WL$_{\mathrm{n+1}}$ aims to shift the charge profile farther from the victim cell and improve program speed to suppress program disturbance degradation ^[14]. This will be further examined in the following detailed analysis. Fig. 2(c) examines the Channel e-Density at the moment of reading the victim cell after program. Compared to when all cells are in the erased state, the electron density of the victim cell is further reduced when the attacking cell is programmed under each pass voltage condition. Detailed examination of the graph reveals that under the 7/7 V pass voltage condition, the e-density at region A is the lowest, followed by 6/6 V, and the highest under 5/9 V. A higher channel e-density at region A indicates a lower bias required to turn on the victim cell, suggesting a lower V$_{\mathrm{th}}$ for the victim cell. Similarly, by applying a pass voltage of 5 V, lower than the existing pass voltage of 7 V, to WL$_{\mathrm{n-1}}$ under the 5/9 V condition, the influence of the channel potential barrier between the attack cell and the victim cell is reduced, as shown in the conduction band. Therefore, the asymmetric pass voltage condition of 5/9 V appears most suitable for improving Z-interference.

Fig. 3 observed the V$_{\mathrm{th}}$ of the attack cell while increasing the program pulse from 10 V to 20 V after the erase state, to measure program speed. Before V$_{\mathrm{pgm}}$ reaches 10 V, the electric field is not applied enough to generate the Fowler-Nordheim (FN) tunneling current from the tunnel oxide to the CTN, so the attack cell remain unprogrammed. Consequently, it's observed that the program speed is fastest under the 5/9 V pass voltage condition, and slowest under the 6/6 V condition. This is because as the pass voltage of adjacent WL decreases, the dispersion effect of the program voltage applied to the select WL towards the adjacent WL direction increases. In other words, as the pass voltage of adjacent WL decreases, the effective electric field applied to the Poly-Si channel underneath the select WL decreases, resulting in a decrease in the amount of charge injected into the CTN, hence reducing the program speed. This decrease in electric field ultimately induces changes in electron charge trap in Fig. 2(b). Therefore, as the pass voltage of adjacent WL decreases under the same program voltage, Z-interference is improved, but the program speed is reduced, so to achieve the same target Vth for the program compared to the 7/7 V pass voltage condition, 6/6 V under pass voltage conditions, a higher program voltage must be applied to the selected WL. Therefore, to maintain the same program operation condition, a higher number of program pulse counts need to be applied during ISPP operation. Additionally, to compensate for the slow program speed characteristic under the 6/6 V condition, when initially setting the program bias during ISPP operation, a higher final program bias needs to be applied, leading to an increase in the probability of FN tunneling due to the degradation of the boosting characteristic of the Poly-Si channel during program Inhibit operation, which may worsen program disturbance ^[17,18].

However, under the 5/9 V condition, the decrease in program speed when applying 5 V can be offset by applying a high voltage of 9 V to WL$_{\mathrm{n+1}}$, thereby improving program speed. To investigate program disturbance due to the V$_{\mathrm{pass}}$ of adjacent WL, the channel boosting potential was compared during program inhibit operation.

Fig. 4 depicts the channel potential when applying the same V$_{\mathrm{pgm}}$ bias of 20 V to the attack cell (WL$_{\mathrm{n}}$) to observe program disturbance. In Fig. 4(a), transitioning from a pass voltage of 7/7 V to 6/6 V results in a decrease in channel potential. This occurs due to a decrease in the pass voltage applied to the cells adjacent to the attack cell, which assists in boosting, leading to a decrease in channel potential and subsequent program disturbance. However, when a pass voltage of 5/9 V is applied, the channel potential is positioned at its highest. When 5 V is applied to WL$_{\mathrm{n-1}}$, a relatively strong turn-off occurs in WL$_{\mathrm{n-1}}$, leading to channel cut-off. Subsequently, the high pass voltage of 9 V applied to WL$_{\mathrm{n+1}}$ assists in boosting, increasing the channel potential and improving program disturb. Fig. 4(b) illustrates the results of channel potential during program inhibit operation with arbitrary program patterns on surrounding WLs. To simulate this, cells are programmed with various V$_{\mathrm{pgm}}$ on the main WL before programming the target cell.

The program was run with the V$_{\mathrm{th}}$ of WL0 being approximately 3 V and the V$_{\mathrm{th}}$ of WL2 being 2.4 V. In this scenario, during verify operation before the program operation, the channel becomes floating due to the increased V$_{\mathrm{th}}$ caused by the pattern. Consequently, due to the down-coupling phenomenon of the floating channel, the channel potential decreases by the amount of the V$_{\mathrm{th}}$ of the adjacent WL, exacerbating program disturbance ^[12]. However, despite this, it can be observed that program disturbance is improved not only with a pass voltage of 5/9 V but also with a pass voltage of 6/6 V. This phenomenon occurs due to the decrease of effective gate voltages (V$_{\mathrm{pass}}$ of WL$_{\mathrm{n-1}}$ cell - V$_{\mathrm{channel potential}}$ of WL$_{\mathrm{n-1}}$ cell) of 0.2 V, -0.2 V, -0.7 V to the victim cell programmed with a V$_{\mathrm{th}}$ of 3 V under conditions of 7/7V, 6/6V, 5/9V, respectively (Table 1). The 6/6 V and 5/9 V pass voltage conditions result in strong channel cut-off due to the relatively lower effective gate voltages, improving off-state leakage current of WL$_{\mathrm{n-1}}$ and preventing the charge sharing between the already down-coupled pre-programmed channel and the channel to be programmed later. Therefore, compared to the case without a program pattern, the overall channel boosting level decreased, but it can be seen that the degree of improvement in channel boosting in the 5/9V condition is greater than that in the 7/7V and 6/6V conditions.

Fig. 5 illustrates the trade-off characteristics of Z-interference and program disturbance when implementing the asymmetric pass voltage method. When all cells are erased, the V$_{\mathrm{th}}$ is approximately -3.5 V. When applying a pass voltage to the WL adjacent to the attack cell (victim cell), if the pass voltage exceeds 10 V, the V$_{\mathrm{th}}$ of the victim cell becomes greater than -3.5 V. In other words, if the pass voltage of WL$_{\mathrm{n+1}}$ is set to 10 V or higher, soft programming of the victim cell occurs, leading to pass disturb. Therefore, it was set to 9 V. When looking at Fig. 5(a) after fixing WL$_{\mathrm{n+1}}$ to 9 V, the channel potential was checked by splitting WL$_{\mathrm{n-1}}$ from 1 V to 9 V. Fig. 5(b) illustrates the trade-off relationship between 1/Z-interference and channel potential under program inhibit operation. In region C, as the pass voltage decreases from 9 V, the channel potential decreases, but Z-interference improves. In region B, it can be observed that the channel potential when a pass voltage of 5 V is applied to WL$_{\mathrm{n-1}}$ is higher than when a pass voltage of 6 V is applied. This indicates that when the pass voltage is below 5 V, the victim cell turns off more strongly due to the channel cut-off condition, thereby alleviating program disturbance ^[10]. In region A, it can be observed that program disturbance worsens again when the pass voltage drops below 4V compared to region C. This is because the lower pass voltage induces down-coupling, pulling down the channel potential of the attack cell. Both Z-interference and program interference are crucial for enhancing device reliability. Therefore, through this TCAD simulation structure, it has been confirmed that setting the pass voltage condition to 5/9V is the optimal condition.

Fig. 2. (a) Changes in victim cell V_th according to attack cell V_th for each pass voltage condition; (b) Distribution of e-trap charge density in the CTN according to each pass voltage condition; (c) Distribution of channel e-density and the conduction band during victim cell read operation after program and corresponding graphs.

Fig. 3. Comparation of program speed of the attack cell under three pass voltage conditions during ISPP operation.

Fig. 4. Comparison of channel potential during program inhibit operation in the inhibit string: (a) without; (b) with a pre-programmed pattern in the string.

Fig. 5. (a) When a pass voltage of 9 V is applied to WLn+1 and WLn-1 splits from 1 V to 9 V, the channel potential is checked in boosting mode; (b) Trade-off relationship between channel potential and 1/Z-interference.

IV. Conclusions

Our investigation into 3D NAND Flash Memory, utilizing asymmetric program-pass voltages, reveals a marked advancement in addressing Z-interference and program disturbances. Employing TCAD simulations, we've applied a lower pass voltage to the victim cell and a higher one to the adjacent cell across from the attack cell, during programming. This strategy significantly mitigates Z-interference by lessening the impact of electron charge from the attack cell on the victim cell. Additionally, it enhances the channel cut-off in the victim cell during program inhibit operations, thereby improving program speed and reducing program disturbances. This advancement not only contributes to the ongoing development of NAND Flash Memory technology but also highlights the critical role of program operation conditions in overcoming the challenges presented by the need for higher storage densities.