1. Operation Voltage Scheme

To find the optimal operation voltage conditions for the proposed structure, technology computer-aided design (TCAD) simulations were conducted with L$_{\mathrm{ch}}$ of 100 nm and T$_{\mathrm{ch}}$ of 20 nm. Fig. 2(a) and (b) illustrate the hole concentrations in the QW body after the write-1 and write-0 operations, respectively, at various operation voltages. As briefly mentioned, the write-1 operation is performed by band-to-band tunneling and the conditions for the write-1 and other operations are summarized in Table 1:

Fig. 2. Hole concentrations in the QW after: (a) write-1; (b) write-0 operations under the different operation voltages.

condition 1: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (-1.0 V, -2.0 V), condition 2: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (-2.0 V, -2.0 V), condition 3: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (-1.0 V, -3.0 V), and condition 4: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (-2.0 V, -3.0 V) were simulated for write-1 operation. Under the conditions 1 and 2 in Fig. 2(a), holes did not accumulate in the QW body. On the other hand, under the conditions 3 and 4, holes were accumulated effectively through band-to-band tunneling. Among the simulated conditions, condition 4 shows a slightly higher hole concentration by a write-1 operation than condition 3. However, when a hold operation starts, the excess holes eventually escape from the QW under the both conditions, keeping the remaining hole concentration similar. Consequently, condition 3 can be chosen for a low-voltage operation. The write-0 operation relies primarily on electron-hole recombination within the floating QW body, and the deep QW constructed by the large VBO provides the predominance to recombination rather than drift and diffusion out of the QW. Thus, a write-0 operation exhibits less voltage dependency, unlike 1T DRAMs with all-Si or alternate material configurations, requiring a sufficient time to erase the holes as can be predicted by Fig. 1(b). When performing a read operation, it is necessary to ensure that the stored holes are not affected. In actual operation schemes for the 1T DRAM, the read operation should have as less effect as possible on the memory state for minimizing the use of refresh operation. Various voltage conditions were evaluated for optimizing the read scheme: condition 1: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (0.3 V, 0.3V), condition 2: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (0.3 V, 0.5 V), condition 3: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (0.3 V, 1.0 V), condition 4: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (0.5 V, 0.5 V), and condition 5: (V$_{\mathrm{GS}}$, V$_{\mathrm{DS}}$) = (0.5 V, 1.0 V). Among these conditions, condition 1 exhibited the smallest change in hole concentration after a read operation, thus showing the least disruptive behavior. When a negative V$_{\mathrm{GS}}$ is applied for hold operation, the depth of QW for hole confinement goes deeper, which makes it hard for the holes to escape from the QW and results in a longer retention time. In this work, a negative V$_{\mathrm{GS}}$ of -0.6 V was applied for conducting hold operation. By controlling V$_{\mathrm{GS}}$ only, no energy is consumed for hold operation. Fig. 3(a) shows the distribution of hole concentration in the hold state after a write-1 operation. The relative locations with reference to T$_{\mathrm{ch}}$ = 20 nm and L$_{\mathrm{ch}}$ = 100 nm are depicted in the horizontal and vertical axes, respectively. A high hole concentration of 10$^{20}$ cm$^{-3}$ is observed beneath the gates on both sides of the channel and the hole concentration at the channel center is as relatively low as 10$^{17}$ cm$^{-3}$. When a write-0 operation is performed, electrons are injected from the source junction into the body so that the number of holes beneath the gate is momentarily reduced down to 10$^{17}$ cm$^{-3}$ level, as shown in Fig. 3(b). Table 1 summarizes the voltage schemes for the respective memory operations of the proposed 1T DRAM.

Fig. 3. Hole distributions in the QW body after: (a) write-1; (b) write-0 operations.

2. Dimension Optimization

To explore how the sensing margin and retention time are influenced by the scaling of device dimensions, L$_{\mathrm{ch}}$ of the 1T DRAM cell was adjusted to 100 nm, 70 nm, 50 nm, and 30 nm, while keeping T$_{\mathrm{ch}}$ constant at 20 nm. Fig. 4(a) through (d) shows sensing margin and data retention at different channel lengths of 100 nm, 70 nm, 50 nm, and 30 nm, respectively. Here, retention time was defined as the elapsed time until the initial difference in read currents between states 1 and 0 is reduced to half so that the original data can no longer be correctly identified. As L$_{\mathrm{ch}}$ gets shorter, the sensing margin increases, but the amount of increase is not large. On the other hand, the retention time drastically decreases with scaling down. As scaling progresses, the electron potential energy of the QW decreases, and consequently, the read current of state 1 increases and the effective depth of QW is reduced, making it easier to lose the confined holes, which shortens the retention time. Nevertheless, with a sufficiently long L$_{\mathrm{ch}}$, the 1T DRAM cell can maintain hole storage for over 1 second, demonstrating a robust retention capability at a L$_{\mathrm{ch}}$ of 100 nm. Fixing L$_{\mathrm{ch}}$ at 100 nm, the effects of T$_{\mathrm{ch}}$ on the sensing margin and retention time are examined in Fig. 5. The retention time is primarily influenced by the VBO, and thus, remains without a notable change. However, the sensing margin is determined by the amount of current, or the number of mobile carriers that make up the read current for state 1, the sensing margin is rapidly reduced. In the following simulations, both L$_{\mathrm{ch}}$ and T$_{\mathrm{ch}}$were fixed at 100 nm and 20 nm, respectively. In Fig. 4(a) through (d) and Fig. 5, retention time is defined as the moment of time at which the initial difference in read currents of state 1 and 0 is reduced to the half value. In the actual array operation, the retention time can be determined by a reference current in an absolute value considering the capability of the sensing circuits, rather than reading by ratio. The sensing margin threatened by the high integration density should be considered in many aspects. Narrowing of sensing margin becomes inevitable as the array density increases, or equivalently, as the number of wordlines (WLs) increases. The critical factors determining the sensing margin in a high-density DRAM array might vary depending on types of sensing schemes. If the conventional voltage sensing scheme is applied, the ratio of cell capacitance to bitline (BL) capacitance can be a critical factor. The cell capacitance of the heterojunction 1T DRAM cell in this work is determined by the change in the amount of charge stored and released by program and erase operations. Thus, the design of QW needs to be further optimized. If the read operation is based on the current sensing scheme, one way of obtaining a clear memory window comes with the minimization of the line resistances. As the portion of potential drop is allocated to the series resistance in the array interconnect with more weight, the memory window genuinely determined by a DRAM cell is buried by the effect of line resistance and gets narrower. The QW volume should be increased for accommodating a larger number of holes for increasing the effective cell capacitance, which can be a smaller technological hurdle since the footprint is not sacrificed with the help of vertical structure of the proposed DRAM cell, which can be a substantial solution in the cell level approach.

Fig. 4. Sensing margin and data retention over time for different L_ch's: (a) 100 nm; (b) 70 nm; (c) 50 nm; (d) 30 nm (T_ch = 20 nm).

Fig. 5. Sensing margin and retention time as a function of channel thickness at a fixed L_ch of 100 nm.

3. High-temperature Operations

As mentioned earlier, a key motivation for this study is to explore the applicability of SiC/Si/SiC QW 1T DRAM in the environments that require high-temperature stability, such as in automotive and power integrated circuits. This is supported by the high melting point and strong breakdown field of 3C-SiC, along with the deep QW created by the large VBO across the 3C-SiC/Si heterojunction. Fig. 6 depicts the transient simulation results over one cycle of the 1T DRAM operations at different temperatures, including 300 K, 358 K, 400 K, and 500 K: write-1/hold/read-1/hold/write-0/hold/read-0/hold. All the currents from write-1, read-1, write-0, and read-0 operations increase as the operating temperature is elevated, and the rate of increase in read-0 current is significantly faster than the rate of increase in read-1 current. Consequently, the large I$_{\mathrm{on}}$/I$_{\mathrm{off}}$ ratio of about 10$^{10}$ at 300 K decreases as temperature increases. At a high temperature, a sharp increase in read-0, or off-state current, is commonly observed. However, the SiC/Si/SiC QW structure successfully limits the read-0 current, even at 500 K, by the precise control over the critical dimensions. As shown in Fig. 7(a) through (d), higher temperatures lead to an increase in the rate of generation and more diffusion of stored holes out of the QW, leading to faster deterioration of retention time and I$_{\mathrm{on}}$/I$_{\mathrm{off}}$ current ratio, accompanying increase in leakage current. However, the deep QW formed by 3C-SiC/Si/3C-SiC heterojunction suppresses the escape of stored holes to source and drain junctions, even at high temperatures. In the QW 1T DRAM, memory state breaking gets faster at a high temperature mainly due to the accelerated diffusion of the carriers occupying the higher energy states in the Fermi-Dirac distribution tail. However, with the 3C-SiC/Si/3C-SiC QW, the programmed holes are more effectively confined and less affected by the temperature elevation. At temperatures above 300 K, even a small gate voltage of -0.6 V can effectively constrain the holes within the QW, resulting in a longer retention time. At 300 K, the proposed device exhibits approximately 30 times wider sensing margin and about 3 times longer retention time compared to Si/Si$_{\mathrm{0.6}}$Ge$_{\mathrm{0.4}}$/Si QW 1T DRAM. At 358 K, the device has more than 10 times larger sensing margin compared with an all-Si 1T DRAM ^[26], and 8 times longer retention time compared with a Si/Si$_{\mathrm{0.6}}$Ge$_{\mathrm{0.4}}$/Si QW device ^[27].

Fig. 6. One-cycle operations at 300 K, 358 K, and 500 K.

Fig. 7. Data retention time and I_on/I_off ratio at different temperatures of (a) 300 K; (b) 358 K; (c) 400 K; (d) 500 K.

4. Viability of the Device Fabrication Processing

A viable process integration can be suggested for higher practicability of a device designed by the series of simulation works. It is crucial to grow high-quality SiC and Si layers on the Si substrate for higher carrier mobility, perfect construction of the quantum well, and absence of interfacial charge effects. There have been a variety of epitaxial growth methods for SiC on the Si platform and chemical vapor deposition (CVD)-based epitaxy has been widely used ^[28]. A presumable series of integrated processes can be schemed for the fabrication of the heterojunction QW 1T DRAM cell in this work as schematically shown in Fig. 8(a) through (f). In Fig. 8(a), the process begins with a Si wafer followed by an epitaxial growth of n$^{+}$ 3C-SiC layer. The SiC layer acts as the source junction and the degenerate n-type doping can be performed in the in-situ manner. Si can be epitaxially grown in the following sequence, with a thickness of 100 nm and a doping concentration of p-type 10$^{17}$ cm$^{-3}$ (in-situ doping with the epitaxy), as shown in Fig. 8(b). Another SiC layer is epitaxially grown for constructing the drain junction (Fig. 8(c)). A thin vertical fin channel can is constructed by an anisotropic dry etch leaving the source junction region for contact as shown in Fig. 8(d). Then, gate oxide and p$^{+}$ poly-Si are sequentially deposited over the vertical fin channel structure as shown in Fig. 8(e). The deposited poly-Si is etched back with a larger amount than the deposited thickness to separate the poly-Si gate and put double gates on both sides of the vertical channel as shown in Fig. 8(f). Here, the etch-back needs to be performed with a high accuracy for determining the location of gate edge, not making an excessive gate underlap from the drain junction end ^[29].

Fig. 8. A presumable process integration for fabricating the proposed heterojunction 1T DRAM cell: (a) Epitaxial growth of n⁺ 3C-SiC on the Si substrate for source junction; (b) p-type Si epitaxy for constructing the vertical channel; (c) Epitaxial growth of n⁺ 3C-SiC on the Si substrate for drain junction; (d) Construction of the vertical thin channel in the fin shape by dry etching; (e) Gate oxide and gate poly-Si depositions; (f) Etch-back of the poly-Si for obtaining a double-gate structure.