| Title |
Vertical Double-gate SiC/Si/SiC Quantum-well 1T DRAM and Its High-temperature Performances |
| Authors |
(Soomin Kim) ; (Seongjae Cho) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.5.483 |
| Keywords |
1T DRAM; 3C-SiC; quantum well; sensing margin; data retention; high temperature |
| Abstract |
In this work, a vertical double-gate 1T DRAM utilizing 3C-SiC/Si/3C-SiC quantum well is proposed to solve the inherent short retention time problem of conventional 1T DRAM. Superior properties of 3C-SiC, such as high thermal conductivity, high critical breakdown field, and large energy bandgap not only improve the retention properties by effectively limiting the mobile charges within the QW, but also contribute to the scalability of DRAM technology in the power electronics and automotive applications. The double-gate structure improves program and erase operation efficiencies, and vertical structure makes a way for high integration density. Emphasizing the performances of the device at high temperature, significant reliability and stability are demonstrated in high temperature environment, which is particularly advantageous for memory devices as well as power devices in the automotive systems. This work shows that 3C-SiC/Si/3C-SiC QW 1T DRAM is a promising candidate for advanced memory technologies achieving wide sensing margin and long data retention even under high-temperature condition. |