I. Introduction

The demand for wide range, low power, low jitter, and high bandwidth frequency synthesizer (FS) is increasing in SoCs based on advanced CMOS nodes. The FS based on fractional N divider can generate arbitrary frequency ^[1]. Unfortunately, the bandwidth of the PLL has to be lowered to reduce quantization noise ^[2,3]. This lower PLL bandwidth leads to increased jitter. Meanwhile, FinFET process provides superior integration density and circuit performance, but the limitation in long transistor channel length and lower supply voltage increases jitter in FS circuits.

Fig. 1 shows generally used fractional-N PLL(FNPLL). In typical FNPLLs, ${\Delta}$${\Sigma}$ modulators (DSM) are used to generate fractional division ratio by switching division values of the multi-modulus divider (MMD). The voltage-controlled oscillator (VCO) output is divided by the MMD and the precise target frequency is set by the DSM.

Fig. 1. Block diagram of the typical fractional N PLL.

Because the division ratio is limited by the integer value, there exists quantization noise which comes from the difference between the values of the ideal fractional value and the integer division value. The noise from the quantization errors is shaped by the DSM. The quantization error generated by the finite steps of the MMD’s divider values are further shaped by the PLL loop bandwidth and DSM ^[4]. By considering only the contribution of DSM noise ${\Phi}$_noise, $_{\Sigma}$$_{\Delta}$(s) and setting all other phase contributors to 0, the phase transfer function to project the phase noise of the DSM to the output of the PLL can be found ^[5] :

(1)

where F(s) represents the Laplace domain transfer function of the loop filter gain. K_phase is charge pump gain and K_VCO represents the voltage to frequency transfer of the VCO.

Fig. 2. Quantization noise effect: (a) No quantization error; (b) N/(N+1) divider; (c) N/(N+1/32) divider.

One solution to reduce jitter is reducing the PLL bandwidth down to tens or hundreds of kHz ^[5]. However, the lower bandwidth has limited loop gain to reduce jitter generated by VCO core and PLL systems. As a result, the output jitter of the FS based on integer MMD is high. Also, the locking time is increased due to the reduced loop bandwidth. Therefore, the integer type MMD may not be the best option for wide range, low jitter fractional-N PLL.

Another way to reduce jitters can be to reduce the amount of the quantization noise ^[6]. Fig. 2(a) shows simulated phase-noise with an ideal fractional divider with 2^nd order DSM. When using N/N+1 dividers, noise from DSM becomes the dominant phase noise source as shown in Fig. 2(b). But if the N/(N+1/32) multi-modulus divider is used, the noise contribution from DSM is reduced and the total noise is close to the ideal fractional divider as shown in Fig. 2(c).

The VCO is one of the key components to reduce jitter. LC and Ring based VCOs are typical choices. LC-VCO has better noise performance compared to the Ring VCOs. But it requires large layout area and has small frequency tuning range. Moreover, using ring VCO has merit for implementing power-efficient transmitter by using multi-phase from it. In this paper, the architecture and circuit technique are presented to implement low jitter fractional divider by using a phase rotating divider and a ring-based multi-phase VCO.

This paper is organized as follows: Section Ⅱ describes the architecture of the proposed FNPLL. Section Ⅲ provides the circuit description of the sub-blocks. Section Ⅳ presents the measurement results. Section Ⅴ concludes this paper.

II. Architecture

Fig. 3 shows the proposed fractional-N PLL. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a VCO, and a fractional frequency divider (FFDIV).

Fig. 3. Block diagram of the proposed fractional-N PLL.

Fig. 4. Phase rotating divider.

The PFD compares the phases of the Fref and two signals and generates an error signal, which drives CP and LF. Then the signal controls VCO. In the proposed architecture, multi-phase of the VCO is used to generate FFDIV output. The FFDIV is composed of a DSM and a phase rotation divider (PRD) and generates fractionally divided feedback clock.

Fig. 4 is an implementation diagram of the phase rotating divider. Total target division ratio is as follows.

(2)

DIVM determines divider ranges, FDIV covers modulus control fractional division ratio. The DSM generates the modulus control parameter of FRACN for integer division ratio and FRACX for fractional division ratio. The resolution of the decimals by FRACX is as follows :

(3)

, where n is the number phases of the VCO, and $2^{r}$ is the minimum phase resolution of the interpolator. For example, if the number of output phases of the phase-controlled oscillator is 8 and the resolution of the phase interpolator (PI) is 4, the value of FRACX may have a multiple of 1/32. If a division ratio of 10 + 1/32 is used, then FRACN=10 and FRACX=1, respectively.

The PRD selects two adjacent phases(CLKI, CLKQ) spaced by 2${\pi}$/n out of VCO’s multiphase phase output clocks and generates a final output phase by interpolating them with a weight factor, ALPHA[3:0].

Fig. 5 shows the diagram of PI controller. In each cycle of divider output clock, FRACX from the DSM generates each phase of phase selection. The current Q/I phase (SELQ_C, SELI_C), the next Q/I phase (SELQ_N, SELI_N) and weighting factors are updated for the phase interpolation shown Fig. 6. The SELI, SELQ uses gray code to limit the changes of the control signal to only 1-bit. After interpolation output clock will have following phase.

(4)

To create a glitch free clock signal, a multi-phase glitch-free phase generator is implemented. This receives current and next Q/I phase information from the PI controller and generates phase shifted output. Basic concept of the glitch-free phase shifting is shown in Fig. 7. A window pulse generated from the current and next phase information with OR operation with MUX_OUT, the glitch during phase shift is removed.

Fig. 5. PI controller diagram.

Fig. 6. Phase interpolator output phase.

Fig. 7. Basic Concept of glitch-free phase shift.

III. Circuit Description

1. Glitch-free Clock Mux

The schematic of glitch-free clock mux is shown in Fig. 8. In every cycle of the output divider, each Q/I clock mux conducts separate phase shift with target amount. From the window generator, a window pulse for removing the glitch from phase shift operation is generated. The resulting glitch-free output clock is delivered to the PI after single to differential conversion for final phase selection.

The clock phases for generating the window pulse are preloaded before phase shift operation by rising edge of the WIN_RST. For Q-phase, the WINDOW rising edge is triggered by the current clock phase selected from I_SELQC[1:0], falling edge by next phase from I_SELQN[1:0]. During the two consecutive flipflop operation, setup time violation could occur when phase difference between current and next clock is under 90 degrees by PVT variation. To eliminate this timing issue, complementary clocks are used for the window falling edge generation. If the clock mux has a phase shift of 0, 90, 180 and 270 degrees, the phase selection for falling edge generation is 180, 270, 180 and 270 degrees, respectively.

A 90 degree phase shift timing diagram for CLKQ is shown in Fig. 9 as an example. When clock phase changes from CLK[0] to CLK[2] , SELQC[1:0] value changes from ``00'' to ``01''.

Fig. 8. Schematic of the deglitch clock mux.

Fig. 9. Timing diagram for 90 degree phase shift.

2. PI

The PI shown in Fig. 10 generates final output phase clock from CLKQ, CLKI of the deglitch clock mux. For the target phase, each Q/I clock phase is selected from CLKQ[3:0] and CLKI[3:0], and the clock mux generates a phase shift clock as shown in Fig. 6.

The mux outputs are then phase-interpolated by the interpolating inverters. The strengths of the interpolating inverters are controlled by the thermometer code ALPHA[3:0]. The interpolating inverters with the inputs CLKQP and CLKQN have the strength of 1-${\alpha}$ while those with the inputs CLKIP and CLKIN have the strength of ${\alpha}$.

The interpolating inverter consists of 4 controllable cells. Controllable cells are selectively enabled by ALPHA[i]. When N controllable cells are enabled for the interpolating inverter with the input CLKIP, (4 ${-}$ N) controllable cells are enabled for the interpolating inverter with the input CLKQP. The output resistance of the PI is determined by the summation of the passive resistor (RPA) and turn-on resistance of the mosfet (RON) which depends on the voltage. For the best PI linearity, power consumption and silicon area, the ratio of RPA/RON is chosen to be 5 while RPA + RON is 6Kohm.

The linearity of the PI is critical in the proposed phase rotating divider, directly deciding the spur level of the PLL. Fig. 11(a) plots the simulated output phase of the PI by control codes. The simulated differential non-linearity (DNL) and integral non- linearity (INL) are below 0.2 least significant bit (LSB) as shown in Fig. 11(b).

The DNL and INL shows a periodic variation across the eight quadrants, the weighting factors applied to adjacent I/Q phases.

Fig. 10. Schematic of Phase Interpolator.

Fig. 11. (a) Output phase; (b) DNL and INL of PI at 3 GHz.

3. Multi Modulus Divider

The proposed FNPLL covers wide range of output frequencies (0.1 GHz-3 GHz) with a reference clock of 10 MHz-150 MHz. Accordingly, a divider with a wide division range (10-125) is needed.

In this work, a MMD and a post divider (PDIV) are used to cover the target division ratio. During dividing operation, PDIV maintains static division ratio, determining division range. While MMD dynamically switches division ratio by the output of the DSM. For example, when target ratio is 35, PDIV operate static division ratio of 3, MMD operates 15 in first cycle, and divide by 10 for the rest of two cycles. By separating divider scheme into two stages, the size of accumulator for the DSM can be minimized, optimizing total area and power consumption.

The architecture of the MMD for achieving programmable division ratio is shown in Fig. 12(a), in which 2/3 pre-scalers are connected like a ripple counter ^[1]. A chain of n bits can produce division ratio of

(5)

This structure covers continuous integer division ratio between 2ⁿ and 2ⁿ⁺¹ -1, which presents a factor of two between the maximum and minimum division ratios. However, this is not sufficient to cover the requirement of factor of six division range for the proposed architecture. Fig. 12(b) shows an improved architecture with the addition of several OR gates, enabling power-of-2 factor by adjusting the effective length of the chain to the required division ratio ^[2].

To reduce jitter from the cascaded asynchronous dividers, the M_OUT signal of the second cell is delivered as output clock to limit the jitter accumulation. The M_OUT signal is clocked at a relatively high frequency and thus the jitter accumulation is only coming from the first cell ^[3].

Fig. 12. Multi-modulus Divider: (a) Basic Architecture; (b) With extended division range.

Fig. 13. Glitch free four-stage MMD.

In the conventional MMD with extended division ratio, all the input signals M_IN of bypassed stage are set to high. Then those 2/3 pre-scaler have no effect on the actual dividing operation but are still working, internal latch status keep changing. So, when the division factor changes across extension boundaries, the first division operation might fail according to the initial values of the 2/3 pre-scalers.

To generate seamless clock edge in the boundary condition, the unused 2/3 pre-scalers are set to reset as shown in Fig. 13 ^[4]. For example, when division ratio switches from 15 to 16, first three of 2/3 pre-scaler should set to work for the division ratio of 15. By the time start div 16 operation, 4th 2/3 pre-scaler becomes activated.

IV. Measurement Results

A prototype ring-VCO based fractional-N PLL is fabricated in 8 nm FinFET CMOS process and its die photograph is shown in Fig. 14. The PLL output clocks are used in the High-Definition Multimedia Interface (HDMI) 2.1 transmitter for serializing data. The designed fractional-N PLL occupies an active area of 0.04 mm². The output frequency range is 0.1 GHz to 3 GHz. To cover wide range operation range, the VCO adopts coarse and fine tuning sequence. Before the PLL is running in closed loop, VCO is set near the target frequency by coarse control loop with 10-bit Frequency control word (FCW). Fig. 15 shows measured output frequency with PVT variation. The prototype is measured using Agilent E4407B spectrum analyzer (SA). The measured phase noise of FNPLL at 3 GHz is shown in Fig. 16(a) and reference spur performance is reported in Fig. 16(b). The integrated jitter from 10 kHz to 100~MHz with 2 MHz of bandwidth is about 1.43ps_rms in integer mode, 1.49ps_rms in fractional-N mode respectively. At 3 GHz total power consumption is 8.5 mW with 0.75~V supply as shown in Fig. 17 (6.7 mW for VCO, 1.5~mW for FFDIV, 0.2 mW for CP and 0.1 mW for bias circuit). Almost all power consumptions are form the VCO to meet jitter requirement for all PVT variations, further power enhancement is expected with VCO enhancement. The performance summary with ring-based FNPLL is shown in Table 1. The proposed architecture achieves FoM_J of -228.8 dB.

Fig. 14. Die photograph.

Fig. 15. VCO frequency measurement result.

Fig. 16. (a) Measured phase noise at 3 GHz output frequency for integer-N and fractional-N modes; (b) Reference spur measurement at 3 GHz.

Fig. 17. Measured power breakdown.

Table 1. Fractional-N PLL Performance Summary

	ISSCC'15 [7]	JSSC'16 [4]	This Work
Technology [nm]	16	65	8
Freq. Range [GHz]	0.25-4.0	2-5.5	0.1-3.0
Ref.Freq [MHz]	50	50	24
Supply [V]	0.52-0.8	0.9	0.75
Power [mW]	3.9	4	8.5
Out Freq. [GHz]	3	5	3
Bandwidth [MHz]	2	5	2
Integrated Jitter [psrms]	3.48 [10 k-1 GHz]	1.9 [10 k-100 MHz]	1.49 [10 k-100 MHz]
FoMJ [dB]*	-228.6	-228.5	-228.8
Area(mm2)	0.029	0.084	0.04

*

V. Conclusions

Ring-based clock generation offers several advantages. Ring oscillators provides wide tuning ranges, inherent multi-phase outputs can be useful for power saving in high-speed interfaces. In this paper, we presented a fractional multi-modulus divider (MMD) which reduces quantization noise by taking the advantage of multi-phase ring oscillator. Fabricated in 8 nm FinFET CMOS process, the prototype generates 3 GHz with 1.49ps_rms integrated jitter which achieves the figure of merit of -228.8 dB.