Mobile QR Code QR CODE

  1. (School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Cheongju, Chungbuk 28644, Korea )

Electro-thermal annealing, degradation, Joule heat, mechanical stress, reliability, 3D NAND flash memory


In contrast to conventional hard disk drive, flash memory storage stores data in NMOS cell transistors which are fabricated on silicon wafer [1]. The gate dielectric of a NMOS cell transistor is composed of tunneling oxide, charge trap layer (CTL), and blocking oxide. As programing (or erasing) voltage is applied to the gate electrode, electrons can be moved between the channel and the CTL. The device structure of a cell transistor has been evolved from two-dimensional (2D) planar FET to three-dimensional (3D) gate-all-round (GAA) FET, as size of is scaled down [2]. However, as gate dielectric of the 3D NAND becomes thinner to pursue better gate controllability as well as faster cell speeds, reliability degradation stemmed from tunneling oxide damage have been severed. In this context, T.-H. Hsu et al., have proposed electro-thermal annealing (ETA) configuration for 3D NAND flash memory. The ETA utilizes the heat generated from the word-line (WL) and enables curing of the tunneling oxide damage [3]. As the tunneling oxide damage is cured by the ETA, degraded retention and endurance characteristics can be recovered. However, even though the ETA is applicable for improving device reliability as well as prolonging device lifespan, device stability in terms of mechanical stress has not been investigated until now. The 3D NAND flash memory is composed of various inorganic materials such as metals, dielectrics, and semiconductor. Hence, mechanical instability associated with thermal expansion of materials, is inevitable [4].

In this paper, mechanical stability during using ETA in 3D NAND flash memory is investigated, for the first time. First, mechanical weakness points are predicted during the ETA based on the temperature distribution and material properties. Then, various guidelines to improve the mechanical stability are proposed in terms of bias configuration and alternative materials for metals and dielectrics. Finally, a novel NAND structure accomplishing metallic layer inside of macaroni oxide, is proposed.


Fig. 1 shows a schematic of A flash memory array. The array consists of multiple strings which are series connected NMOS transistors along the bit-line (BL) direction, as well as pages along WL direction. Among them, a single string was investigated to avoid excessive calculation during simulation. Fig. 2 shows back-bone structure of a 3D NAND string for simulation. COMSOL Multiphysics simulator was used with Joule heating and solid-mechanics modules. The reason for using the COMSOL is because it is the most useful tool for analyzing mechanical stress in nano-scaled devices. The structure contains a BL and 10$^{\mathrm{th}}$ floored WLs consisted of tungsten, Si-substrate, inter-layer dielectric (ILD), and charge trap layer (CTL) consisted of SiO$_{2}$ / Si$_{3}$N$_{4}$ / Al$_{2}$O$_{3}$. During simulation, temperature of the Si-substrate and heat flux during convective cooling, were assumed to room temperature (20 $^{\circ}$C) and 10 W/m·K, respectively. Maximum temperature and mechanical stress were extracted at the planes cut along for each WL. Detailed device structure and material information for simulations are summarized in Table 1 [5]. Typically, high temperature above 600 $^{\circ}$C are required to activate the ETA for NAND flash memory in a short time [3,6]. However, unwanted melting or thermally assisted electromigration of metallic layers can be triggered when the temperature is excessively high [7]. Hence, 3.5 mA of current flow was intentionally applied to a 10th WL, as shown in Fig. 2(b).

Fig. 1. Basic schematic of a NAND flash memory array.
Fig. 2. (a) Schematic of a NAND flash memory string used for simulation studies; (b) Cross-sectional image of the Fig. 2(a) with bias conditions for ETA.
Table 1. Device dimensions and material parameters for 3-dimensional (3D) simulation of mechanical stability


Size [nm]

Coefficient of thermal


${\beta}$ [1/K]



${\kappa}$ [W/m·K]



${\sigma}$ [S/m]

Word-Line (WL)


(L$_{\mathrm{W}}$ ${\times}$ L$_{\mathrm{D}}$ ${\times}$ L$_{\mathrm{H}}$)

160 ${\times}$ 160 ${\times}$ 20

4.5 ${\times}$ 10$^{-6}$


20 ${\times}$ 10$^{-6}$

Bit-Line (BL)

100 ${\times}$ 100 ${\times}$ 100



(L$_{\mathrm{W}}$ ${\times}$ L$_{\mathrm{D}}$ ${\times}$ L$_{\mathrm{H}}$)

250 ${\times}$ 250 ${\times}$ 50

2.6 ${\times}$ 10$^{-6}$


1 ${\times}$ 104

Poly-Si Channel Thickness



2.6 ${\times}$ 10$^{-6}$


3 ${\times}$ 10$^{3}$

Inter-Layer Dielectric (ILD) Thickness



0.5 ${\times}$ 10$^{-6}$


1 ${\times}$ 10$^{-12}$

Blocking Oxide Thickness



6.5 ${\times}$ 10$^{-6}$


1 ${\times}$ 10$^{-12}$

Charge Trap Layer Thickness



2.3 ${\times}$ 10$^{-6}$


1 ${\times}$ 10$^{-12}$

Tunneling Oxide Thickness



0.5 ${\times}$ 10$^{-6}$


1 ${\times}$ 10$^{-12}$

However, reducing the 3.5 mA of current is much desirable considering power consumption. It is possible to reduce the power by modification of device structure as well as materials [8].


At first, thermal analysis was performed, as shown in Fig. 3(a). The Si-substrate played role as heat sink hence it was observed that the temperature during ETA was the highest at the 10$^{\mathrm{th}}$ WL, but lowest at the bottom WL. The temperature of WLs was linearly decreased with 62 $^{\circ}$C / WL, as shown in Fig. 3(b). In terms of cross-sectional plane of a WL, the temperature was the highest at tungsten gate, but lowest at Si$_{3}$N$_{4}$ layer which has the highest thermal conductivity among the SiO$_{2}$ / Si$_{3}$N$_{4}$ / Al$_{2}$O$_{3}$. layer (Fig. 3(c)). It was also confirmed that as the applied power increases, the generated temperature increased, as shown in Fig. 3(d).

Fig. 4(a) shows simulated mechanical stress profile i.e., Von Mises stress which is representative stress of nanostructure, during the ETA under the bias condition of Fig. 3. Similar with the temperature profile, the mechanical stress during ETA was the highest at the 10th WL, but relatively stable at the bottom WL, as shown in Fig. 4(b). In this context, it can be confirmed that the mechanical stress during the ETA is coincide with the cell temperature.

In terms of cross-sectional plane of a WL, the most vulnerable material by mechanical stress during the ETA, was blocking oxide composed of Al$_{2}$O$_{3}$, and followed by tungsten, Si$_{3}$N$_{4}$, and tunneling oxide (Fig. 4(c)). The material stress is closely related to the coefficient of thermal expansion of each material composing a cell, as shown in Fig. 4(d). In this context, the mechanical stress of the Al$_{2}$O$_{3}$ is the most vulnerable during the ETA because of its sensitive thermal expansion characteristic.

Fig. 3. (a) Simulated heat distribution profile when 3.5 mA of current is applied to 10$^{\mathrm{th}}$ WL for ETA of 3D NAND flash memory; (b) Extracted cell temperature along BL direction; (c) Extracted temperature along the WL direction at the 10$^{\mathrm{th}}$ WL; (d) Extracted cell temperature with various applied power for ETA.
Fig. 4. (a) Simulated mechanical stress distribution profile when 3.5 mA of current is applied to 10$^{\mathrm{th}}$ WL for ETA of 3D NAND flash memory; (b) Extracted Von Mises stress along BL direction; (c) Mechanical stress distribution profile along at the 10$^{\mathrm{th}}$ WL; (d) Extracted Von Mises stress according to materials composing a single WL.

In contrast to the Fig. 3 and 4 showed the case when ETA is applied to 10$^{\mathrm{th}}$WL, the Fig. 5(a) shows mechanical stress when the ETA is performed through the middle of a string. It was observed that there was volume expansion in the middle of string where ETA was performed. Fig. 5(b) shows extracted cell temperature. The temperature was the highest at the middle of the string, but lowered as far away from the middle, as shown in Fig. 5(b). The mechanical stress showed identical profile with the temperature, as expected (Fig. 5(c)).

Fig. 6(a) and (b) shows extracted mechanical stress and cell temperature when 3.5 mA of current is flowed through the 1st WL. The temperature was the highest at the 1$^{\mathrm{st}}$ WL, but lowered as far away from the upper side, as shown in Fig. 6(b). Fig. 6(c) shows extracted mechanical stress during the ETA. Even though, the mechanical stress was the highest at the 1st WL, the extracted values along the BL were lower than the case of Fig. 5(c).

When ETA is performed to multiple WLs simultaneously, a lot of cell transistors can be recovered at once. Fig. 7 shows extracted mechanical stress and cell temperature when currents are flowed through the 1st, 6th and 10th WLs, at the same time. However, as the summation of applied power increases, the temperature as well as the mechanical stress increases too much compared to the other cases. In other word, ETA using multiple WLs should be avoided for the better stability of NAND flash memory string.

Fig. 5. (a) Simulated mechanical stress distribution profile when 3.5 mA of current is applied to a 6$^{\mathrm{th}}$ WL for ETA; (b) Extracted temperature; (c) mechanical stress along BL direction.
Fig. 6. (a) Simulated mechanical stress distribution profile when 3.5 mA of current is applied to a 1$^{\mathrm{st}}$ WL for ETA; (b) Extracted temperature; (c) mechanical stress along BL direction.
Fig. 7. (a) Simulated mechanical stress distribution profile when 3.5 mA of current is applied to 1st, 6th and 10th WLs for ETA; (b) Extracted temperature; (c) mechanical stress along BL direction.

Fig. 8 summarizes mechanical stress with various bias configurations of the ETA. The mechanical stress was at least 1.5 times lower when the current was applied to a single WL rather than simultaneously applied to multiple WLs. In addition, it was also confirmed that the Flash memory showed better mechanical stability when the ETA is applied to the WL at bottom owing to the lower annealing temperature.

Fig. 9 shows extracted mechanical stress with respect to alternative WL materials instead of tungsten. The electrical and thermal properties of each metal are summarized in Table 2. When titanium is deposited instead of tungsten as WLs, there is at least 2.8 times higher temperature compared to other metals such as aluminium or tantalum. The reasons can be explained in two ways. First, the lower electrical conductivity generates the higher temperature during the ETA [9]. Second, the low thermal conductive material increases thermal isolation among the other WLs. In this context, the string is mechanically stable when the aluminum is applied. While the string is mechanically unstable when the titanium is deposited for WLs.

Fig. 10 shows extracted cell temperature and mechanical stress according to the thermal conductivity of inter layer dielectric (ILD) SiO$_{2}$. It was confirmed that as thermal conductivity of ILD is high, the generated heat can be easily dissipated during ETA. In other word, the heat can be diffused to the upper or lower layers. As expected, extracted mechanical stress was also stable when the thermal conductivity of the ILD is low (Fig. 10(b)).

Fig. 8. Summary of mechanical stress according to bias configuration of the ETA in 3D NAND flash memory.
Fig. 9. Extracted (a) cell temperature; (b) mechanical stress with various alternative WL materials when ETA is applied the 10$^{\mathrm{th}}$ WL.
Fig. 10. Extracted (a) cell temperature; (b) mechanical stress with various ILD materials when current of 3.5 mA is applied to 10$^{\mathrm{th}}$ WL for ETA.
Table 2. Summary of electrical and thermal properties of metal gates

Coefficient of thermal expansion, ${\beta}$ [1/K]

Thermal conductivity, ${\kappa}$ [W/m·K]

Electrical conductivity, ${\sigma}$ [S/m]













Fig. 11 shows novel structure of a sting to relieve the mechanical stress during ETA. Additional metallic layer is inserted inside of macaroni oxide. Radius of the metallic pillar was assumed to 21 nm. The metallic pillar showed at least 1.4 times lower the temperature as well as at least 1.68 times lower mechanical stress compared to the case without metallic layer. As a result, the metallic pillar in a 3D NAND string is applicable for suppression of self-heating effect [10], enabling back-biasing [11], and even decreasing mechanical stress. However, it should be noted that fabrication of the metallic pillar is very difficult considering current dry etching and deposition technologies.

Fig. 11. (a) Schematic of proposed 3D NAND flash memory string; (b) Cross-sectional image of the proposed structure with bias conditions for ETA; (c) Comparison of cell temperature; (d) mechanical stress when current of 3.5 mA is applied 10$^{\mathrm{th}}$ WL for ETA.


Mechanical stability during ETA in 3D NAND flash memory was investigated. As cell temperature during the ETA increases, the mechanical stress also increases due to thermal expansion of materials. Several guidelines with respect to bias configuration, WL materials, ILD materials, and novel string structure, were proposed to improve the mechanical stability. In terms of bias configuration, applying the ETA to a single WL is preferred. Moreover, it was more stable when a WL near the Si-substrate is utilized for the ETA. In terms of materials of the WLs and the ILDs, using highly thermal conductive material are preferred. Finally, metallic layer inserted inside of macaroni oxide is recommended for lower cell temperature as well as mechanical stress.


This work was supported by the National Research Foundation (NRF) of Korea grant funded by the Korea government (MSIT) (No. 2021R1F1A1049456). Y.-J. Kim and J.-Y Park are with the School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Cheongju, Chungbuk 28644, Republic of Korea. Corresponding author is J.-Y. Park (


Compagnoni C. M., Goda A., Spinelli A. S., Feeley P., Lacaita A. L., Visconti A., Sept. 2017, Reviewing the Evolution of the NAND Flash Technology, Proc of the IEEE, Vol. 105, No. 9, pp. 1609-1633DOI
Aochi H., 2009, BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices, IEEE International Memory Workshop (IMW), pp. 1-2DOI
Hsu T.-H., Lue H.-T., Du P.-Y., Chen W.-C., Yeh T.-H., Lo R., Chang H.-S., Wang K.-C., Lu C.-Y., May 2019, Study of self-healing 3D NAND flash with micro heater to improve the performances and lifetime for fast NAND in NVDIMM applications, IEEE 11th International Memory Workshop (IMW), pp. 1-4DOI
Lee K.-S., Park J.-Y., Jun. 2021, Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs, Electronics, Vol. 10, No. 12, pp. 1395DOI
Jung W.-J., Park J.-Y., Oct. 2021, Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory, Micromachines, Vol. 12, No. 11, pp. 1297DOI
Lue H.-T., Du P.-Y., Chen C.-P., Chen W.-C., Hsieh C.-C., Hsiao Y.-H., Shih Y.-H., Lu C.-Y., Dec. 2012, Radically extending the cycling endurance of flash memory (to > 100 M cycles) by using built-in thermal annealing to self-heal the stress-induced damage, in Proc. IEEE Int. Electron Devices Meeting (IEDM), pp. 9.1.1-9.1.4DOI
Park J.-Y., Moon D.- I., Seol M.-L., Jeon C.-H., Jeon G.-J., Han J.-W., Kim C.-K., Park S.-J., Lee H.-C., Choi Y.-K., Jan. 2016, Controllable electrical and physical breakdown of poly-crystalline silicon nanowires by thermally assisted electromigration, Sci. Rep. Art. no. 19314DOI
Kim M.-K., Choi Y.-K., Park J.-Y., Jan. 2022, Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs, Micromachines, Vol. 13, No. 1DOI
Park J.-Y., Moon D.-I., Seol M.-L., Kim C.-K., Jeon C.-H., H.-Bae , Bang T., Choi Y.-K., Mar. 2016, Self-curable gate-all-around MOSFETs using electrical annealing to repair degradation induced from hot-carrier injection, IEEE Trans. Electron Devices, Vol. 63, No. 3, pp. 910-915DOI
Park J.-Y., Yun D.-H., Kim S.-Y., Choi Y.-K., Feb. 2019, Suppression of Self-Heating Effects in 3-D V-NAND Flash Memory using a Plugged Pillar-Shaped Heat Sink, IEEE Electron Device Lett., Vol. 40, No. 2, pp. 212-215DOI
Jung D.-H., Lee K.-S., Park J.-Y., Oct. 2021, Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND, J. Semicond. Technol. Sci., Vol. 21, No. 5DOI
Yu-Jin Kim

Yu-Jin Kim is currently pursuing the B.S. degree from the School of Electronics Engineering, Chungbuk National University, Cheongju, Republic of Korea. Her current research interests include the simulation of semiconductor devices.

Jun-Young Park

Jun-Young Park received the B.S. degree from the School of Electrical and Electronic Engineering, Yonsei University, Seoul, Republic of Korea, in 2014, and the M.S. & Ph.D. degree from the Korea Advanced Institute of Science and Technology, Daejeon, Republic of Korea, in 2016 and 2020. He is currently the Assistant Professor of School of Electronics Engineering, Chungbuk National University, Cheongju, Republic of Korea. His current research interests include reliability of semiconductor devices.