https://doi.org/10.5573/JSTS.2025.25.2.109

(Minseon Park) ; (Min-Woo Kwon)

Biological neurons play a crucial role in preventing excessive activation of the human brain and enabling efficient information processing by balancing excitatory and inhibitory functions. Neuromorphic chips and hardware based Spiking neural networks (SNNs) aim to replicate these biological neural systems in hardware. For instance, in artificial neural networks, biological neurons are represented by neuron circuits. Conventional analog neuron circuits utilize CMOS technology. However, existing CMOS-based analog neuron circuits show significant issues related to power consumption and area. Additionally, they fail to effectively integrate both excitatory and inhibitory functions. Therefore, in this study, we propose a neuron circuit that integrates both Neuronal excitatory and inhibitory functions using feedback field-effect transistor (FBFET). We fabricated the FBFET using TCAD Athena Simulation and designed the neuron circuit using SPICE mixed-mode simulations. By utilizing the threshold voltage adjustment characteristics of the FBFET’s control gate, we successfully inhibited neuron firing. Ultimately, we succeeded in integrating both excitatory and inhibitory signals using a single FBFET device. This work represents a significant advancement toward realizing bio-inspired neuromorphic computing systems.

https://doi.org/10.5573/JSTS.2025.25.2.117

(Soomin Kim) ; (Md. Hasan Raza Ansari) ; (Seongjae Cho)

Recently, GeSn has been identified as a promising candidate for group-IV-driven electronic and photonic devices owing to its high carrier mobility and indirect-to-direct bandgap transition property. In this work, a comprehensive study of primary material characteristics, including electron affinity, bandgap energies at local minimum valleys, and effective density of states (DOS) of the GeSn alloy, has been conducted as a function of Sn fraction and in-volume stress. As the Sn fraction increases, leading to the transition from an indirect-to-direct bandgap, the electron affinity rises sharply, while the energy bandgap and the effective DOS decrease. Based on these material parameters, an n-type metal-oxide-semiconductor field-effect transistor has been designed and optimized in terms of DC parameters and high-frequency performance as a function of Sn fraction and the corresponding in-volume biaxial stress in the channel region. As tensile stress or Sn fraction increases, both the on-state (Ion) and off-state currents (Ioff) rise due to a narrowed bandgap energy, while the subthreshold swing (S) value also degrades. In contrast, compressive strain reduces Ioff. Finally, the incorporation of GeSn channel is reported to be advantageous for high-speed operation.

https://doi.org/10.5573/JSTS.2025.25.2.123

(Yeji Lee) ; (Arati Kumari Shah) ; (Myounggon Kang) ; (Seongjae Cho)

In this paper, we present the hardware implementation and performance analysis of the digital equivalent of an integrate-and-fire (I&F) neuron model using the field-programmable gate array (FPGA) technology. Inspired by the human brain, the I&F neuron model is crucial for achieving energy-efficient neuromorphic systems. The digital implementation was performed on a Zynq multiprocessor system-on-chip (MPSoC) FPGA using the Xilinx Vivado Design Suite, replacing analog components with their digital counterparts. Simulation and implementation results demonstrated the ability of the model to accurately replicate the spiking behaviors of biological neurons while utilizing minimal FPGA resources. Specifically, the design used only 0.01% of the available lookup tables and flip-flops, ensuring a compact and efficient implementation. The total on-chip power consumption was measured to be 0.71 W, with a junction temperature of 25.7 ?C. These results validate the functionality and performance of the digital I&F neuron model and highlight its potential for integration into fully CMOS-based spiking neural networks. The compact design of the model, combined with low power consumption, makes it a promising candidate for scaling into larger and more complex neuromorphic computing systems.

https://doi.org/10.5573/JSTS.2025.25.2.128

(Hee-Jae Oh) ; (Dong-Ik Oh) ; (Hyun-Seop Kim) ; (Ho-Young Cha)

The monolithic integration of a driving integrated circuit (IC) with a micro-light-emitting diode (microLED) offers the advantage of transfer-free integration between the LED and the driving IC. A p-GaN/AlGaN/GaN heterojunction platform was employed to fabricate the monolithically integrated driving IC within individual microLED pixels. A 2T1C driving IC, featuring enhancement-mode GaN transistors and a metal-insulator-metal (MIM) capacitor, was designed and monolithically fabricated on a single wafer. The prototype micro-LED pixel with the integrated driving IC demonstrated successful operation, with fast rise and fall times of 20 ns and 50 ns, respectively

https://doi.org/10.5573/JSTS.2025.25.2.134

(Myung-Hyun Baek)

With the growing demand for faster data processing and enhanced computational performance, DRAM technology faces increasing challenges as cell dimensions shrink below 10 nm. This study focuses on two critical phenomena in vertical DRAM structures: the Pass Gate Effect (PGE) and Gate-Induced Drain Leakage (GIDL). We perform comprehensive 2D Technology Computer-Aided Design (TCAD) simulations to analyze the impact of aggressor cell activation on victim cell barrier modulation. Additionally, we investigate the effect of floating body structure on GIDL. Our results indicate that the absence of a Back Gate (BG) significantly exacerbates PGE, while integrating a BG effectively suppresses this effect. These results emphasize the importance of the BG in mitigating inter-cell interference and improving the overall performance of DRAM.

https://doi.org/10.5573/JSTS.2025.25.2.142

(Jeong Hun Song) ; (Sang Won Yoon)

Large language models (LLM) and generative artificial intelligence (AI) require extensive data processing and fast data transfer between components, increasing interest in high bandwidth memory (HBM). The high-speed data processing capability of HBM drives the need for next-generation HBM with additional dynamic random access memory (DRAM) layers. However, this increased stacking leads to more severe thermal issues, along with higher power consumption, potentially limiting HBM performance. This study explores these thermal challenges through 3D finite element analysis (FEA) simulations of simplified HBM models incorporating non-conductive film (NCF) layers. Three models with 4, 8, and 12 DRAM layers were simulated and compared. The results show that the maximum simulated temperature reaches 80?C, close to the maximum allowable DRAM temperature, and approaches 110?C, exceeding the recommended operational temperature for HBM. Therefore, this study highlights the potential thermal limitations of highly stacked HBM configurations.

https://doi.org/10.5573/JSTS.2025.25.2.148

(Ji Yong So) ; (Young Doo Yoon) ; (Sang Won Yoon)

The automotive industry is advancing toward eco-friendliness, with an increasing number of xEV models entering the market. This shift drives demand for high-performance power semiconductors, leading to greater power density and heat generation, which challenge the thermal performance of xEV power modules, which is the core energy-conversion component. To address these challenges, advanced module cooling structures, such as direct single-sided and double-sided cooling (DSC), have been developed. However, most DSC power modules rely on indirect cooling using thermal interface materials (TIMs), whose low thermal conductivity limits thermal performance improvements despite the use of complex 3D structures. This study investigates the impact of TIM characteristics on the thermal resistance of power modules. Finite element analysis (FEA) simulations demonstrate an obvious reduction in thermal resistance with enhanced TIM conductivity, revealing a performance saturation point beyond a certain conductivity level. These findings would provide valuable insights for TIM design targets.

https://doi.org/10.5573/JSTS.2025.25.2.154

(Jung Su Yoon) ; (Sang Won Yoon)

Warpage is a critical issue in semiconductor packages, particularly in molded packages, which are affected by several factors, including shrinkage of epoxy molding compounds (EMCs) during curing and mismatches in coefficients of thermal expansion (CTEs) between adjacent components. This study investigates the impact of EMC properties on the warpage of a power semiconductor module and the feasibility of reducing warpage by appropriately selecting EMC materials. Moldex3D simulation software was used to analyze the combined effects of EMC shrinkage and CTE mismatch. The simulation results show that the thermal conductivity and CTEs of the EMC have a significant impact on package warpage, which can be reduced by 29% with the right selection of EMC. As an additional approach, embedding cooling pins in the EMC encapsulation, anticipating enhanced thermal dissipation and mechanical resistance, was proposed, and an additional ∼ 10% reduction in warpage was demonstrated.

https://doi.org/10.5573/JSTS.2025.25.2.160

(Junpyo Lee) ; (Byoung-Gue Min) ; (Jongmin Lee) ; (Dongmin Kang) ; (Hyungtak Kim)

In this work, we evaluated the thermal resistance of AlGaN/GaN-on-SiC High Electron Mobility Transistors (HEMTs) with different GaN buffer thicknesses. The thermal resistance was derived by correlating the decrease in ID.SAT values under both self-heating and external-heating conditions with pulsed I-V measurements. The experiments were carried out with a short duty cycle (0.1%) to minimize heating during the measurement state. ID.SAT decreases as the channel temperature increases by dissipated power or elevated external temperature, respectively. By matching the ID.SAT values from these two conditions, we determined the channel thermal resistance. The thin buffer GaN device demonstrated a lower thermal resistance, indicating that a thinner buffer layer aids in more efficient heat dissipation to the substrate.

https://doi.org/10.5573/JSTS.2025.25.2.166

(Tae-Gu Kang) ; (Jin-Ku Kang)

In pulse amplitude modulation 4-level (PAM-4) receiver design, the variation of the effective least significant bit (LSB) threshold voltage degrades the margin of LSB decision and worsens the bit error rate (BER). This paper proposes a dynamic comparator to solve the problem. The proposed dynamic comparator features low variability in effective LSB threshold voltage due to its common-mode-rejection capability. The proposed dynamic comparator has been designed and simulated at post-layout level in a 45 nm CMOS with 1.1 V supply voltage. The effective LSB threshold voltage variations of the conventional and proposed dynamic comparators are quantitatively analyzed and compared by simulation results.

https://doi.org/10.5573/JSTS.2025.25.2.176

(Young Gi Kim) ; (Sung Hoon Bae) ; (Bo-Seong Kang) ; (Hyeong Jun Jang) ; (Jae-Yeon Hwang) ; (Patrick Roblin)

This paper presents a 65 nm CMOS divider circuit that (1) operates as a divider with a division ratio of 64 based on digital logic when the DC supply voltage is low and (2) operates as a multi-band injection-locked frequency divider (ILFD) with a unique division ratio for each band of operation when the supply voltage is high. The proposed divider consists of a six-stage cascade of current-mode logic (CML) dividers with buffer circuits. The frequency span of operation in the ILFD mode is divided into 7 sub-bands from 2 to 27 GHz depending on the supply voltage. The proposed circuit demonstrates a record 528 ILFD division ratio with a low power consumption of 0.926 mW, which is the best performance reported so far in the literature. A phase noise of-102.27 dBc is measured at 100 kHz offset for a 27.113 GHz input signal

https://doi.org/10.5573/JSTS.2025.25.2.184

(Quang-Huy Do) ; (Tan-Binh Ngo) ; (Sang-Woong Yoon)

We demonstrated a non-magnetic non-reciprocal circulator in CMOS integrated circuit (IC) technology using a four-path band-pass filter (BPF)-based staggered commutation network, which can break Lorentz reciprocity and replace a ferrite-based circulator used for decades in the history of wireless communication. The circulator IC was implemented in Samsung 28 nm RF CMOS process. The small-signal measurements among three ports showed the minimum insertion loss of 4.5-5.5 dB, and the maximum isolation of 35.7-44.8 dB in the frequency of 2.39-2.4 GHz. The measured maximum IP1dB and minimum noise-figure were 18.5 dBm and 5.8 dB, respectively. The circulator IC consumes 21.6 mW, and the size of the chip without pads is 0.93 mm2 .

https://doi.org/10.5573/JSTS.2025.25.2.191

(Byeong Yong Kong)

In this paper, a fault-tolerant algebraic interleaver architecture is presented for interleave division multiple access (IDMA) systems operating in harsh environments. Since the multiuser detection procedure is performed chipby-chip according to an interleaving pattern, it is of paramount importance to keep track of the current index at all times. To protect the interleaving index in a register from soft errors, an encoder and a decoder associated with an error-correcting code are added. Moreover, to mitigate the latency overhead of such an architecture, the encoder is merged with an essential logic that precomputes the next index. As a result, the proposed interleaver tolerates soft errors while suppressing the latency overhead.