https://doi.org/10.5573/JSTS.2024.24.6.501

(Changmin Song) ; (Young-Chan Jang)

A high-speed receiver including an auto-skew calibration circuit for 10 Gb/s mobile industry processor interface (MIPI) D-PHY is proposed to support data communication of high-performance cameras using four data lanes and one clock lane. The proposed auto-skew calibration circuit, consisting of a delay line and skew control blocks for data and clock, supports skew calibration for predetermined training data while also supporting skew calibration for random data not defined in the MIPI D-PHY. It performs a phase comparison between the clock and the data for skew calibration, which uses only the rising edge of the data instead of the rising and falling edges of the clock as the reference signal. The delay line used in the skew calibration circuit uses a delay cell consisting of three NANDs consuming 1.41 mW at full delay. The proposed MIPI D-PHY receiver including the auto-skew calibration circuit is designed by using a 28-nm CMOS process with a supply voltage of 1.0 V. The proposed MIPI D-PHY receiver circuit receives 2.5 Gb/s of data per data lane for a total of 10 Gb/s of data and consumes 0.4 mW/Gbps/lane. The proposed auto skew calibration circuit improves the data skew from 148 ps to 19 ps and from 230 ps to 18 ps for the predetermined training and random data, respectively.

https://doi.org/10.5573/JSTS.2024.24.6.511

(Taehyeon Kim) ; (Kinam Song) ; (Kihyun Kim) ; (Kyoungho Lee) ; (Jonghyun Kim) ; (Sungsik Lee) ; (Inho Kang)

This paper presents an experimental methodology to precisely estimate the junction temperature of commercial SiC power MOSFETs. To achieve this, the current-voltage characteristics and forward voltage drift of body diode were measured for various gate biases coupled with various ambient temperatures by using in-house test equipment. From those experimental data, we estimated the effect of the gate bias and sensing time on the sensitivity and the sensing voltage drift of SiC power MOSFETs. These results show that the sensitivity and sensing voltage drift exhibited different aspects with respect to gate bias (VGS). It is also found that the sensitivity was decreased with increasing the sensing current (ISENS) for VGS ≤ 5 V whereas increased for VGS > 5 V. However, the sensing voltage drift is found to be monotonically increased with ISENS for all the cases of the gate bias. We believe that this is attributed to a higher trap density at the SiC/SiO2 interface.

https://doi.org/10.5573/JSTS.2024.24.6.518

(Chanyoung Kim) ; (Junghyup Lee) ; (Minyoung Song)

Ingestible sensors are pivotal in monitoring the gastrointestinal (GI) tract and enhancing comprehension of complex gastrointestinal processes, propelled by sensor technology advancements. They must ensure robust wireless communication from deep within the body while maintaining longevity for comprehensive monitoring. Wireless system miniaturization stands as a promising solution to these challenges. This paper introduces the current state and technical challenges ingestible sensors and their solutions for wireless system miniaturization. The key techniques for further miniaturization include the antenna miniaturization, integration of adaptive impedance matching networks, and the replacement of crystal. Additionally, the paper explores future directions for wireless communication systems to support the continued advancement of ingestible sensor technology.

https://doi.org/10.5573/JSTS.2024.24.6.532

(Soonseong Hong) ; (Hyojun Yoo) ; (Donghoon Choi) ; (Hyouk-Kyu Cha)

This paper proposes a low-power, low-noise neural recording analog front-end (AFE) integrated circuit (IC) for bidirectional neural interface system-on-chips (SoCs). The proposed AFE signal conditioning chain offers flexibility to support both local field potentials and action potentials through adjustable gain and bandwidth. The AFE also integrates an active common-mode cancellation loop (CMCL) that can tolerate common-mode stimulation artifacts up to 1 Vpp. The CMCL circuit can be controlled by comparators and logic circuits to operate only when large artifacts are present. Implemented using a 0.18-μm CMOS process, the measured overall voltage gain range of the entire AFE is 40 dB to 60 dB. The high-pass cutoff frequency is adjustable from sub-1 Hz to 500 Hz, and the lowpass cutoff frequency is switchable from 280 Hz to 10 kHz. For 1-10 kHz frequency range, the measured integrated input referred noise (IRN) is 2.12 μVrms when CMCL is disabled, while the IRN is 3.29 μVrms with CMCL enabled. The total power consumption of the proposed AFE is 2.6 μW at 1-V supply voltage.

https://doi.org/10.5573/JSTS.2024.24.6.540

(Yunseong Jo) ; (Jaeduk Han)

This paper presents a four-level pulse amplitude modulation (PAM-4) transmit driver utilizing the tailless current-mode structure. The PAM-4 driver operates at 24 Gb/s with a 1.3-V supply voltage, leveraging the advantage of the tailless approach. The low output impedance inherent to the tailless current-mode drivers is enhanced using a gain-boosting technique. The prototype chip was fabricated using a 14-nm FinFET process, achieving a vertical eye-opening of 44.6 mV at 24 Gb/s while consuming 60.3 mW. It achieved an energy efficiency of 2.513 pJ/bit. Through the gain boosting technique, the output impedance increased by approximately 100%.

https://doi.org/10.5573/JSTS.2024.24.6.547

(Hyeon-Sik Ahn) ; (Chae Hong) ; (Yoonseuk Choi) ; (Piljae Park) ; (Jusung Kim)

This work proposes an ultra-wideband (UWB) radar receiver front-end implemented with a low cost 0.13 μm CMOS technology. The proposed receiver front-end is a cascaded configuration of a low-noise amplifier (LNA) with single-differential conversion and a two-stage radio frequency variable gain amplifier (RFVGA) to ensure a sufficient signal strength and quality over the various radar reception distance. The LNA is constructed with noise-cancelling common gate (CG)-common source (CS) amplifier for wideband input matching and single-to-differential conversion. Two-stage RFVGA successively corrects the differential gain and phase imbalance and provides regenerated gain by the back-to-back inverters employed at the cascode and output node of each stage. The frequency response of LNA and RFVGA are staggered. Subsequently, the broadband spectrum of 6-to-9 GHz are covered with low pass response of LNA, high-pass and bandpass response of each VGA stages. Simulation results show that the maximum and minimum voltage gains are 26 dB and 13 dB, respectively, while consuming only 12 mW of power from a 1.2 V supply. The prototype circuit operates at a minimum noise figure (NF) of 8.72 dB and a third-order intercept point (IIP3) of -8.4 dBm.

https://doi.org/10.5573/JSTS.2024.24.6.557

(Jongmin Lee) ; (Jang Hyun Kim)

This paper investigates the electrical characteristics of work-function variation (WFV) in dopingless Tunnel Field-Effect Transistor (TFETs) with SiO2-Si3N4-SiO2 (ONO) gate insulator stacks. It explores the potential benefits of using ONO structures to mitigate WFV's impact on the channel. The study also examines the immunity of TFETs to WFV and current variations compared to doping-based junctions. The paper begins by discussing the challenges introduced by increased doping concentrations, specifically poly/metal-grain granularity (MGG). The proposed dopingless TFET with an ONO stack structure is introduced, acknowledging the need for rigorous validation. Detailed information on device simulation and programming sequences for TFETs is provided. The mixed-signal circuit configuration is outlined, focusing on the use of high-performance MOSFETs and TFETs to enhance output voltage margins and reduce transition time variations. The study concludes by presenting the electrical characteristics of WFV and its impact on TFET devices. The effectiveness of program adjustments in reducing threshold voltage (Vt) scatter for both n-type and p-type TFETs is discussed. In summary, this study explains the advantages and limitations of dopingless TFETs with ONO stack structures, offering insights into their application.

https://doi.org/10.5573/JSTS.2024.24.6.565

(Hyeon Seo Yun) ; (Jong Kyung Park)

In this study, we address both Z-interference and program disturbance in 3D NAND Flash Memory by proposing an innovative asymmetric program-pass voltage technique. Utilizing Technology Computer-Aided Design (TCAD) simulations, our approach applies varying pass voltages to adjacent word lines, effectively reducing Z-interference and program disturbances. This method enhances cell reliability and performance, marking a significant advancement in 3D NAND Flash Memory technology. Our findings emphasize the critical role of program operation conditions in memory design, offering a viable solution to the challenges posed by increased storage density demands.

https://doi.org/10.5573/JSTS.2024.24.6.572

(Sungju Ryu) ; (Jae-Joon Kim)

Sparsity-aware neural processing units have been studied to exploit computational skipping on less important features in the neural network models. However, neural network layers typically show various matrix densities, so the hardware performance varies depending on the layer characteristics. In this paper, we introduce a reconfigurable comparator-multiplier architecture, so we can dynamically change the number of comparator/multiplier modules. The proposed reconfigurable architecture increases the throughput by 1.06-17.00× compared to the previous sparsity-aware hardware accelerators.

https://doi.org/10.5573/JSTS.2024.24.6.578

(Gwangmyeong An) ; (Seungmyeong Yu) ; (Jongchan An) ; (Junyoung Song)

The proposed digital low-dropout voltage regulator (DLDO) automatically controls clock frequency based on the difference between the reference and feedback voltage. Enabling adaptive frequency regulation during voltage ringing events, and thus assisting rapid transient response. Unlike prior approaches utilizing two voltage-controlled oscillators (VCOs) to generate frequencies for controlling pass gates, this work employs a single VCO, reducing the need for VCO control voltage pins. The proposed DLDO regulates the output at 1 V from a 1.2 V supply and has been implemented based on a 65 nm CMOS process. The transient time is 782 ns, a power efficiency of 99.93%, and the FOM is 15 fs.