https://doi.org/10.5573/JSTS.2025.25.5.469

(SuMin Oh) ; (HyunJin Kim)

Analog circuit optimization remains a challenge due to its high-dimensional design space and the prohibitive cost of simulations. To improve sample efficiency, we propose a reinforcement learning (RL) framework that uses intrinsic rewards, enabling agents to efficiently explore novel circuit designs. Furthermore, by leveraging a conditional variational autoencoder (CVAE) for reconstruction-based intrinsic reward, our approach enhances exploration and accelerates convergence in circuit optimization. Experimental results on practical circuits demonstrate significant performance improvements over counterparts without using a reconstruction-based intrinsic reward.

https://doi.org/10.5573/JSTS.2025.25.5.476

(Ha-Neul Kim) ; (Saukinta Thapa) ; (Sun-Hye Kim) ; (Na-Young Lee) ; (Jong-Yoon Kim) ; (Yeong-Cheol Kim)

This study elucidates the sublimation behavior of molybdenum hexacarbonyl (Mo(CO)6) based on abinitio thermodynamic calculations. The sublimation temperature of solid Mo(CO)6 at 1 atm was calculated to be 385 K. In addition, the initial reaction mechanism of Mo(CO)6 on the β-cristobalite SiO2(111) surface was analyzed. Among the considered dissociation pathways, the CO2-forming pathway, involving the interaction between a CO ligand and a surface oxygen atom, was found to be the most thermodynamically favorable.

https://doi.org/10.5573/JSTS.2025.25.5.484

(Hye Yun Seong) ; (Sung Hyun Yoon) ; (Young Hoon Lee) ; (Gwang Min Yoon)

The rapid advancement of high bandwidth memory (HBM) technology introduces significant challenges in metrology due to its complex 3D stacked die architecture. Conventional measurement and inspection tools, optimized for planar DRAM wafers, fail to accurately assess critical die-to-die alignment parameters such as die shift and tilt, particularly post-bonding. This paper presents a novel metrology methodology leveraging infrared (IR) imaging combined with advanced image processing algorithms to overcome these limitations. A dual-scan system captures both base wafer fiducials and top die patterns, enabling precise alignment measurement within stacked HBM assemblies. Edge enhancement using Sobel filtering and normalized cross-correlation (NCC) techniques facilitate robust pattern recognition and sub-pixel alignment, addressing challenges posed by low contrast and IR resolution constraints. Experimental validation on production-grade HBM wafers demonstrates superior recognition rates and measurement repeatability, establishing the proposed approach as a reliable and efficient solution for next-generation semiconductor metrology. The integration of IR optics and sophisticated algorithmic processing significantly improves inspection coverage, contributing to enhanced yield and manufacturing robustness in advanced 3D memory technologies.

https://doi.org/10.5573/JSTS.2025.25.5.490

(Intae Whoang) ; (Byung Yoon Lim) ; (Kijun Bang) ; (Sang Un Lee)

At SK hynix’s wafer level package (WLPKG) line, a passivation SiN layer is deposited to prevent Cu diffusion in through silicon via (TSV), followed by a tetraethyl orthosilicate (TEOS)-based SiO2 layer deposition to ensure TSV robustness during planarization of protruded TSVs. With the increasing demand for high bandwidth memory (HBM), the TEOS SiO2 deposition process became a throughput bottleneck due to the chamber configuration of the existing CVD equipment. To enhance productivity, process optimization was pursued to improve the deposition rate while maintaining the film properties required for subsequent processes. Recipe modifications were evaluated under mass production conditions, with a focus on deposition rate, film uniformity, and potential risks such as particle generation and CMP removal rate (R/R) changes that could impact TSV yield. Increasing TEOS flow initially improved the deposition rate by up to 78% but caused TSV damage due to higher CMP R/R at wafer edges. By optimizing O2 flow, He-carrier flow, and chamber pressure, film robustness was enhanced, and final adjustments reduced TEOS flow to achieve a 46% rate improvement without significant R/R variation. The optimized recipe increased CVD process capacity by approximately 25%, meeting both productivity and quality stability requirements for high-volume HBM manufacturing.

https://doi.org/10.5573/JSTS.2025.25.5.496

(Yoo Bin Song) ; (Min Woo Ryu) ; (E-San Jang) ; (Kyung Rok Kim)

We report a high-performance plasmonic terahertz (THz) detector based on a monolithic transistorantenna (Trantenna) structure by using the 28-nm CMOS foundry technology. By designing an ultimate asymmetric field-effect transistor (FET) on a confined channel structure with shallow trench isolation (STI) technology, enhanced channel charge asymmetry between the source and drain has been obtained compared to the non-confined channel structure with limitations of asymmetric boundary condition intensification. In addition, we experimentally demonstrate a 2.25-fold performance enhancement over the non-confined channel plasmonic THz detector at 0.1 THz.

https://doi.org/10.5573/JSTS.2025.25.5.502

(Woo-Seok Kim) ; (Kwan Yong Lee) ; (Sang Hun Yeo) ; (In Jun Jang) ; (Young-Eun Choi) ; (Min Woo Ryu) ; (Kyung Rok Kim)

We propose a highly scalable ternary CMOS (T-CMOS) technology using halo implantation in commercial 28-nm process. By forming a locally confined halo profile, VDS-dependent constant band-to-band tunneling (BTBT) current is successfully obtained which enables VDD-scalable subthreshold ternary operation. The merged halo profile near source/drain junction exhibits excellent short-channel behavior and facilitates the suppression of the tunneling current with a reduced ion dose than retrograde one, while maintaining the same VT design. Halo energy and tilt angle are introduced as additional design knobs to further reduce the tunneling current, expanding the T-CMOS design window. Therefore, low-power ternary operation is demonstrated in a wide-bias range from 1.0 V to 0.3 V, with sub-picoampere level leakage. By leveraging an additional VDD/2 latch state that enables 1.5-bits per cell storage in a high-density 6T bitcell, our T-SRAM achieves 0.62 pW/bit leakage power and nearly a 10× improvement in the figure-of-merit (cell density / leakage power) over prior reported low-leakage SRAMs.

https://doi.org/10.5573/JSTS.2025.25.5.509

(Soyhan) ; (Jeong Min Baik) ; (Yunsik Lee)

Hexamethyldisiloxane (HMDSO) presents a significant challenge to the reliability of metal-oxidesemiconductor (MOS) gas sensors due to its deactivation properties, posing risks to environmental and daily life safety. This study enhances the performance of MOS gas sensors by developing an anti-poisoning sensor (APS) with a composite CeO2-rGO (Cerium Oxide-reduced Graphene Oxide) layer on Pd/ZnO nanoparticles. The APS improves resistance to HMDSO poisoning during hydrogen (H2) detection and extends the sensors’ lifespan. Previous work was referenced for this study, and experimental sensing results demonstrate that the APS sensor shows a notable 1.25% change in resistance/conductivity when exposed to air and HMDSO (10 ppm) at 250?C, surpassing both Pd/ZnO and ZnO sensors. Surface modifications with CeO2-rGO effectively mitigate HMDSO-induced deactivation mechanisms, inhibiting the formation of organosilicon compounds, silicates, and a SiO2 layer on metal/metal-oxide surfaces that typically reduce sensor sensitivity over time. CeO2 supplies oxygen, influencing surface chemical reactions, while rGO acts as a barrier preventing HMDSO infiltration, thereby protecting the sensing layer’s integrity. The aim of these APS a material system is to enhance the lifespan and reliability of electrochemical sensors (ECS) for future applications in the detecting of food spoilage gases in refrigerator environments.

https://doi.org/10.5573/JSTS.2025.25.5.517

(Wenjie Yang) ; (Yanning Chen) ; (Dong Zhang) ; (Fang Liu) ; (Yang Zhao) ; (Fang Ni) ; (SongChao Zhu) ; (Xiangyu Meng)

In order to solve the problems of low efficiency of capacitive array layout design and parasitic effects affecting the matching degree in high-precision SAR ADCs, this paper proposes an automatic placement and routing method for capacitive digital-to-analog converter (CDAC) based on EDA technology. By routing the bottom plate beneath the bottom metal of the capacitor and integrating the shield structure, the parasitic coupling effect between the top plate and the bottom plate is significantly reduced. Combined with the co-centroid layout and the inter-bit staggered arrangement strategy, the horizontal parasitic coupling of adjacent capacitor bottom plates is effectively suppressed. The algorithm adopts a layered routing mechanism, uses Metal3 and Metal4 to realise the separation of horizontal and vertical routing, and optimises the matching characteristics by dynamically adjusting the intercolumn distribution of capacitors, and the effective number of bits (ENOB) can increase by up to 0.38 bits after adding a shielding layer. Experimental results show that the layout generation time of the proposed method is only 0.85-14.26 seconds, the ENOB can reach 99.20%-99.77% of the ideal value in the 8-13 bit CDAC design. This method realises the second-level automatic generation of high-precision capacitor arrays, and provides an efficient EDA solution for high-performance ADC design.

https://doi.org/10.5573/JSTS.2025.25.5.530

(Kyungkyun Kang) ; (Seulbee Yang) ; (Giang Truong Le) ; (Hanho Lee)

CRYSTALS-Kyber is a lattice-based post-quantum cryptosystem that is resistant to attacks by quantum computers and was selected for standardization in the NIST PQC round-3 process. In 2023, NIST published Federal Information Processing Standard (FIPS) 203 for ML-KEM, which includes a set of algorithms (Key Generation, Encapsulation, and Decapsulation) as the next version of CRYSTALS-Kyber. However, the performance and design flexibility of ML-KEM still need to be evaluated. Our system presents a high-performance and fast HW/SW codesign implementation of ML-KEM based on the NIST PQC round-3 parameters using the Vivado HLS tool. HLS tools offer various optimization benefits through the use of directives to accelerate hardware modules. Point-wise multiplication, addition, and parallelism are incorporated in the design to accelerate time-consuming operations in both AES-GCM IP and ML-KEM IP. All hardware modules are parameterized, enabling full support for runtime configuration to increase versatility. Moreover, the proposed HW/SW architecture and tightly coupled operational workflows reduce data transmission overhead between the processor and hardware modules. The hardware accelerator is implemented using reconfigurable logic on an FPGA and is integrated with a high-performance ARM Cortex-A53 processor in the Xilinx Zynq UltraScale+ architecture, supported by the PYNQ framework. To evaluate the performance of the proposed HW/SW system for ML-KEM at NIST security levels 1, 3, and 5, we used various data types, including video (AVI, H.264), images (8-bit and 24-bit color), and text files. For a fixed input size of 320 kB, the proposed hybrid cryptosystem based-on ML-KEM PQC achieved an average of 11.3× improvement in execution time compared to software implementation, with runtimes of 605 ms and 6,894 ms, respectively

https://doi.org/10.5573/JSTS.2025.25.5.542

(Kihun Kim) ; (Woo-Young Choi)

Light detection and ranging (LiDAR) technology, which leverages light instead of radio waves as the source, offers superior resolution and resistance to jamming, making it a promising alternative to radio detection and ranging (RADAR) for 3D imaging and object detection. Silicon photonics-based optical phased arrays (OPAs) enable non-mechanical beam steering, overcoming the limitations of traditional rotating LiDAR systems. In OPAs, optical phase shifts are realized with the driver IC, which provides the necessary analog voltages to the optical phase shifters. This paper presents a 32-channel OPA driver IC designed to achieve high linearity and enhanced channel-to-channel uniformity. The proposed IC integrates an 8-bit digital-to-analog converter (DAC) based on an R-2R ladder, a high-gain rail-to-rail amplifier, and an I2C serial interface to support scalable multi-chip operation up to 128 channels. Key design strategies include layout optimization of resistors and MOSFETs within the driver to reduce mismatch and improve channel consistency under process variations. Fabricated in a 180 nm CMOS process, the proposed IC delivers monotonic DAC operation with a worst-case differential nonlinearity (DNL), which quantifies the deviation in step size between adjacent codes, of 0.52 least significant bits (LSB), and an integral nonlinearity (INL), which measures the deviation of the DAC transfer function from an ideal straight line, of 0.81 LSB, validating its process-robust design. Beamforming simulations using measured DAC performance demonstrate minimal performance degradation, with less than 0.2% main lobe intensity loss and negligible side lobe suppression ratio degradation. These results confirm that the proposed driver IC is suitable for robust and scalable OPA-based LiDAR systems.

https://doi.org/10.5573/JSTS.2025.25.5.548

(Seungjun Lee) ; (Garam Kim)

In the field of CMOS image sensors (CIS), achieving high resolution while maintaining cost efficiency is a critical challenge. As the demand for high-resolution images in mobile devices continues to grow, preserving cost efficiency in the manufacturing process is increasingly important. To achieve this, it is necessary to extend the source follower (SF) to shorter channels. However, reducing the length of SF channels leads to a decrease in gain, which is a major source of nonlinearity in CIS. This paper presents a comprehensive study on the linearity of SF gain, with an analysis of gain performance through technology computer-aided design (TCAD) modeling and simulation. Compared to conventional n-type metal-oxide-semiconductor field-effect transistors (NMOS) SF, tunnel field-effect transistor (TFET) SF demonstrate superior gain and linearity, although the miniaturization process also results in a significant reduction in gain for TFET SF. To address this, we have analyzed gain improvement through structural optimization of TFET SF. Consequently, the optimized TFET SFs exhibit enhanced gain, and we propose the use of an optimized TFET as the pixel SF to significantly improve the linearity performance of CIS.

https://doi.org/10.5573/JSTS.2025.25.5.556

(Seon Woo Kim) ; (Kyung Min Shin) ; (Jong Kyung Park)

Hybrid bonding technology, integrating Cu-Cu metal bonds and dielectric-dielectric materials, has emerged as a promising solution for high-density, high-performance semiconductor packaging. This study proposes a novel equivalent circuit model for a 4-metal hybrid bonding structure, designed to accurately represent electrical resistance, including contact resistance, in dual damascene hybrid bonding configurations. Finite Element Method (FEM) simulations were conducted to validate the model under varying structural and process parameters such as via count, height, resistivity, and contact resistivity. The proposed model demonstrated high accuracy, with discrepancies below 1% when compared to FEM results. Additionally, experimental validation was performed using fabricated devices with varying via dimensions and metal thicknesses, further confirming the model’s robustness and precision. The proposed model effectively predicts resistance behavior, providing a reliable and efficient tool for optimizing hybrid bonding structures in advanced semiconductor devices.

https://doi.org/10.5573/JSTS.2025.25.5.564

(Jinchan Wang) ; (Wenshuai Liu) ; (Huanqing Peng) ; (Jingyu Chang) ; (Jiahao Yao) ; (Kexin Wang) ; (Jincan Zhang)

In this paper, a small-signal modeling method for InP Heterojunction Bipolar Transistors (HBTs) based on the Grey Wolf Optimizer-Support Vector Regression (GWO-SVR) algorithm is proposed. As a branch of Support Vector Machines (SVM), Support Vector Regression (SVR) is a rigorous mathematical model for regression prediction developed through extensive theoretical derivation and verification. However, its performance is limited by the selection of the penalty factor and kernel function, making manual optimization difficult and unreliable. To address this issue, the Grey Wolf Optimizer (GWO) is employed to optimize the penalty factor and kernel function parameters of SVR. By constructing a GWO-SVR model, automatic optimization within a predefined range is achieved to predict the small-signal characteristics of InP HBTs. Comparative experiments demonstrate that the proposed model achieves excellent prediction performance. Under the optimal parameters obtained by GWO, the small-sample characteristics of GWO-SVR in predicting the small-signal behavior of InP HBTs are verified, indicating its effectiveness and accuracy in handling limited training data.

https://doi.org/10.5573/JSTS.2025.25.5.576

(Young-Hwan Lee) ; (Jae-Geun Lim) ; (Hyung-Jung Kim) ; (Jae-Hyuk Lee) ; (Seong-Bo Park) ; (Seong-U Choi) ; (Joo-Yeol Yang) ; (Jun-Ho Boo) ; (Gil-Cho Ahn)

This paper presents an 8.3-MHz second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC). To achieve an ideal second-order noise transfer function (NTF), an integrator combining an amplifier with a ping-pong switched-capacitor (SC) is used. By sharing the amplifier between two integrators, the design reduces the area of the loop filter. Implemented in a 28 nm CMOS process, the prototype achieves a bandwidth of 8.3 MHz while operating at a 100 MHz with an oversampling ratio (OSR) of 6. It achieves a signal-to-noise and distortion ratio (SNDR) of 66.1 dB, and a dynamic range (DR) of 69.8 dB while consuming 2.93 mW from a 1 V supply. The resulting Schreier figure-of-merit (FoMS) is 160.6 dB, and the Walden FoM (FoMW) is 107.0 fJ/conversion-step. The active die area occupies 0.101 mm2 .

https://doi.org/10.5573/JSTS.2025.25.5.585

(Sangyeop Lee,Junghwi Kim) ; (Intae Whoang) ; (Hongjae Jeong) ; (Gitae Moon) ; (Sunghyun Yoon) ; (Younghoon Lee) ; (Gwangmin Yoon) ; (Sangyup Lee)

Advanced Packaging (AP) is driving innovation beyond the limits of traditional Moore’s Law scaling. Among various advanced packaging technologies, High-Bandwidth Memory (HBM) is gaining significant attention for next-generation semiconductors. As the number of stacked layers in high-bandwidth memory increases, wafer and chip warpage become critical quality factors directly impacting yield and reliability. However, there is currently no equipment or method for direct in-line measurement of chip warpage, as ultra-thin wafers are bonded to carrier wafers during handling, making warpage measurement in this state meaningless. This paper presents the world’s first research on a direct, large-scale, non-destructive chip warpage measurement process applicable in in-line manufacturing. We developed a novel measurement method based on specialized process treatments and hardware modifications. Experimental validation confirmed the accuracy and reliability of the proposed approach. The resulting high-volume chip-level warpage data showed a strong correlation with actual measurements, demonstrating that the method provides highly meaningful data for mass production applications. The results of this study have been implemented into measurement equipment and developed into a commercialized solution currently in use.

https://doi.org/10.5573/JSTS.2025.25.5.598

(Minh Le) ; (Son Ngoc Truong)

Neuromorphic computing, utilizing memristor crossbar arrays offers a promising solution for edge device by enabling cognitive tasks such as pattern recognition, thanks to its small size, low power consumption and in-memory processing capability. Among various memristor architectures for neuromorphic computing, the single crossbar stands out due to its efficiency in terms of power and area saving when performing the pattern recognition task based on the Exclusive-NOR operation. However, this architecture exhibits performance instability when handling sparse data. To overcome this limitation, this work proposes an enhanced single crossbar architecture that integrates a column-wise constant current generating circuit to enable the full-XNOR functionality. This design preserves the advantages of the baseline single crossbar design while substantially improving robustness to sparse data. Simulation results, evaluated with images of varying data densities (0.25, 0.5, and 0.75), demonstrate the addition of the constant term elevates the column currents uniformly, allowing the Winner-take-all circuit to function efficiently and produce correct outputs. When the data density drops below 0.3, the proposed single memristor crossbar with a column-wise constant term maintains a 100% recognition rate, whereas the architecture without the constant term experiences significant degradation, with recognition rate dropping to as low as 0%. The proposed single memristor crossbar architecture with constant column-wise term overcomes the limitation of the baseline single crossbar design introduced in previous study, while retaining its key advantages. Specifically, it reduces the number of memristors by 50%, and achieves recognition accuracy improvements of 7% and 4% under a 10% device defects rate, and 11.4% and 3.3% under the 40% memristance variation, compared to the complementary and the twin crossbar architectures, respectively.

https://doi.org/10.5573/JSTS.2025.25.5.610

(DaeRyong Shin) ; (SuMin Oh) ; (WanSoo Kim) ; (HyunJin Kim)

In this work, we present a novel adaptive testing method based on convolutional neural networks (CNNs). We propose a conversion method of test patterns into spectral images using the fast Fourier transform (FFT), which enables consistent dimensionality across various circuits and allows the CNN to extract frequency-domain features. Moreover, we investigate the effect of different types of spectral images by comparing a single-channel magnitude image with a multi-channel image that includes magnitude, real, and imaginary parts. Experimental results on the ISCAS ’85 benchmark circuits show that the proposed method achieves over 95% accuracy with a maximum of 97% reduced parameters compared to MLP and conventional CNNs. Therefore, we demonstrate the effectiveness and scalability of the proposed method for adaptive testing.

https://doi.org/10.5573/JSTS.2025.25.5.616

(Sung-Hoon Cho) ; (Myunglae Choo) ; (Byung-Guen Lee)

A hybrid delta-sigma (?Σ) modulator is proposed to achieve additional second-order noise shaping via feedback paths consisting of the 1-bit fine quantizer output (DFine) and integrated residues. A 5-dB noise suppression is obtained through digital cancellation using DFine without causing noise leakage. In a 180-nm CMOS process with a sampling rate of 12 MHz and oversampling ratios (OSRs) of 16 and 32, the ?Σ modulator achieved signal-tonoise and distortion ratios (SNDRs) of 92.9 and 96.7 dB and power consumption of 1.3 mW from a 1.8-V supply, showing improved noise suppression and power efficiency.