https://doi.org/10.5573/JSTS.2024.24.5.393

(U Jin Cho) ; (Youhyeong Jeon) ; (Sung Wook Park) ; (Min-Woo Kwon)

This paper presents a proof of concept that combines a nano-composite hydrogen detecting sensor and machine-learning technique to achieve accurate and fast detection of hydrogen leakage. The nano-composite hydrogen detecting sensor is fabricated by depositing MoS2 on a SiO2/Si wafer using chemical vapor deposition, followed by forming discrete Pd nanoparticles through DC (Direct current) sputtering. This sensor shows high sensitivity of 2.77 and fast response time of 4 to 5 seconds at room temparature, but has a significant dependency on environmental factors such as temperature, and humidity. A machine learning technique, i.e. random forest, was incorporated to filter out the environmental factors. Experimental results show that the combination, i. e. MiCS-2714 sensor not only retains sensitivity, response time of the nano-composite but also attains R2 score of 0.994, MSE 0.0506, and the state classification accuracy of 0.979.

https://doi.org/10.5573/JSTS.2024.24.5.399

(Kyoung-Il Do) ; (Jin-Woo Jung) ; (Hee-Guk Chae) ; (Jooyoung Song) ; (Chan-Hee Jeon) ; (Sukjin Kim)

This study proposed a dual silicon-controlled rectifier (SCR)-based protection device with an enhanced structure and high holding voltage for protection against electrostatic discharge (ESD). The structure facilitates an electrical connection between the bridge and additional N+ diffusion regions to turn on an additional NPN parasitic bipolar transistor on the SCR loop path and reduce the SCR positive feedback loop gain. Consequently, the snapback characteristics of the conventional device were improved. A two-dimensional technology computer-aided design (TCAD) simulation was performed to verify the operating principles and identify the characteristics of this device. Subsequently, the proposed device and a low-trigger dual-directional (LTDD) SCR were fabricated using a 0.18 μm bipolar-CMOS-DMOS (BCD) process under identical conditions. Further, the transmission-line-pulse (TLP), transient latch-up (TLU) measurement method, and hot-chuck control system were used to evaluate the electrical characteristics and thermal reliability. In addition, the electrical characteristics of the device were optimized utilizing design variables. The measurement results indicated that the proposed device exhibited an improved holding voltage of 11.31 V, which was further optimized to 14.24 V using a suitable design parameter. Moreover, it demonstrated sufficient thermal reliability with a holding voltage greater than 12 V at 500 K. Therefore, this device is suitable for 12-V-class applications and is expected to provide excellent area-based efficiency and thermal reliability.

https://doi.org/10.5573/JSTS.2024.24.5.410

(Monalisa Pandey) ; (Aminul Islam)

Memory circuits in the space environment are susceptible to stability and reliability issues caused by charged particles such as α-particles, heavy-ions, electrons, and photons. These particles can create an ion track inside the memory device, leading to an upset in the storage bit. This poses a significant problem for conventional 6T SRAM, which is unable to tolerate such upsets. To address this issue, several authors have proposed radiation-hardened SRAM cells to mitigate the upset problem. This paper proposes a 12 transistor-based SRAM cell, the performance parameters of which have been compared with the other referenced memory cells like conventional 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO SRAM cells. The proposed design exhibits high resilience to radiation disturbances. Additionally, it boosts a critical charge (QC) of 1.6 fC, positioning it as a highly favorable option for deep space applications. The proposed 12T shows higher read stability which is validated by RSNM. Our proposed design shows 2×, 1.6×, 1.4×, and 1.2× higher RSNM than that of the 6T, QUATRO 10T, QUCCE 12T and WEQUATRO SRAM cells. The proposed cell also exhibits lower hold power consumption compared to QUATRO 10T (0.86×), QUCCE 12T (0.40×), and WEQUATRO (0.74×), respectively. Similarly, in terms of area overhead proposed 12T consumes smaller area than WEQUATRO and QUCCE 12T, respectively. Major design metrics such as critical charge (QC), write ability (determined by Combined Word Line Margin (CWLM)), read stability (determined by RSNM), Hold Power dissipation (HPWR), Read Access Time (TRA), Write Access Time (TWA), area, etc., are conflicting in nature (meaning one can be improved at the expense of another). Therefore, a new design metric called Electrical Quality Metric (EQM) has been developed based on these design metrics. The proposed 12T SRAM cell exhibits the highest value of EQM, proving its superiority to other comparison SRAM cells.

https://doi.org/10.5573/JSTS.2024.24.5.424

(Mujun Choi) ; (Deokkeun Oh) ; (Juho Kim)

Clock tree synthesis (CTS) has become a critical step in designing the high performance synchronous system. The clock gating technique is one of the well-known methods for reducing power consumption. However, it may cause bias temperature instability (BTI)-induced Vth degradation of clock buffers and asymmetric aging resulting in large clock skew. In this paper, we propose a novel symmetrical buffered clock tree synthesis with supply voltage alignment to handle BTI. As the first step, a symmetrical abstract tree topology with minimized power consumption is generated in bottom-up stage. Second, the top-down stage estimates asymmetric BTI caused by clock gating with signal probability. Prior to the placement step, the linear programming (LP)-based algorithm is applied to find optimal supply voltages to buffers at each tree level while satisfying clock skew constraints. Finally, wire routing is performed using wire snaking to complete the clock tree synthesis. Experimental results show that the proposed CTS achieves on average 51% reduction in clock skew compared to existing CTS methods.

https://doi.org/10.5573/JSTS.2024.24.5.440

(Taek-Joon An) ; (Ook Kim) ; (Jeong-Mi Park) ; (Jin-Ku Kang)

This paper proposes a multi-phase ring oscillator based fractional-N phase locked loop (FNPLL) frequency synthesizer using phase interpolator for high-speed serial link. This paper aims to reduce quantization noise by employing sub-integer divider, extending PLL bandwidth. Fabricated in 8 nm CMOS process, the proposed FNPLL operates over wide frequency range of 0.1-3 GHz. The proposed FNPLL achieves 1.49 ps rms integrated jitter at 3 GHz output. The proposed FNPLL achieves wide BW up to 2 MHz using a 25 MHz reference clock.

https://doi.org/10.5573/JSTS.2024.24.5.448

(Kyeongjun Kim) ; (Seonghearn Lee)

Based on the analysis of the RF inductive effect due to the negative capacitance observed in the -parameter of floating body PD-SOI n-MOSFETs on the Smith chart, the reason why this effect appears at a much higher than the DC kink voltage , unlike in body contact devices, is revealed for the first time. The origin of the anomalous -dependence on RF inductive effect is identified by analyzing the - dependent kink conductance and the pole frequency , which are extracted using the frequency curves of the output admittance. Using the measured versus data, which is validated by a physical body transconductance equation, it is confirmed that the turning radius of the -parameter is reduced at lower due to a decrease in . It is theoretically proven that the extracted data is reduced as decreases, and if is less than the minimum measurement frequency, the rotation angle of the trajectory becomes significantly smaller. Due to the decrease in and at lower the anomalous RF inductive effect is exhibited in floating body devices.

https://doi.org/10.5573/JSTS.2024.24.5.459

(Sanghyun Lim) ; (Donghun Cho) ; (Jaehee You)

To reduce the large amount of memory required in image processing, high image quality memory data compression/decompression algorithms are proposed to eliminate the upper bits that overlap between neighboring pixels by the addition of simple hardware without image quality degradation inherent in conventional lossy compression. In addition, a method to maximize compression rates is discussed based on look-up tables, considering the human visual system. According to the characteristics of the frame image, a programmable architecture is proposed to compute proposed compression/decompression methods as well as run-length encoding and also conventional lossless algorithms. Also, compression rates and performances for SOP implementation are evaluated with the design and simulation of the proposed compression memory circuits.

https://doi.org/10.5573/JSTS.2024.24.5.473

(Young-Ha Hwang)

This paper evaluates circuit techniques that enhance the display noise immunity in the analog front-end of mutual-capacitive touch systems and discusses corresponding design issues. Demonstrated through behavioral-level circuit simulations based on Verilog-A with electrical modeling of a capacitive touchscreen panel, the following three points are highlighted: Firstly, a high-voltage driving scheme at the transmitter improves the signal-to-noise ratio (SNR) by directly enhancing the signal power. However, the SNR improvement could be limited by residual chopping timing errors. Secondly, the signal frequency for capacitance modulation should be properly selected to avoid the display-data-dependent fundamental tone and harmonics of the display noise interference. Lastly, a fully differential sensing scheme at the receiver has a limitation in rejecting the common-mode component of display noise interference coupled into the receiver due to the channel-to-channel mismatch in the TSP, especially capacitance mismatches.

https://doi.org/10.5573/JSTS.2024.24.5.483

(Soomin Kim) ; (Seongjae Cho)

In this work, a vertical double-gate 1T DRAM utilizing 3C-SiC/Si/3C-SiC quantum well is proposed to solve the inherent short retention time problem of conventional 1T DRAM. Superior properties of 3C-SiC, such as high thermal conductivity, high critical breakdown field, and large energy bandgap not only improve the retention properties by effectively limiting the mobile charges within the QW, but also contribute to the scalability of DRAM technology in the power electronics and automotive applications. The double-gate structure improves program and erase operation efficiencies, and vertical structure makes a way for high integration density. Emphasizing the performances of the device at high temperature, significant reliability and stability are demonstrated in high temperature environment, which is particularly advantageous for memory devices as well as power devices in the automotive systems. This work shows that 3C-SiC/Si/3C-SiC QW 1T DRAM is a promising candidate for advanced memory technologies achieving wide sensing margin and long data retention even under high-temperature condition.

https://doi.org/10.5573/JSTS.2024.24.5.491

(Iraj Moghaddasi) ; (Byeong-Gyu Nam)

Nowadays, deep neural networks (DNNs) are being applied for safety-critical applications such as automotive and aerospace while emphasizing the high significance of lifetime resilience. Conversely, hardware accelerators have been employed for the efficient execution of complex DNNs on edge devices with resource constraints. Meanwhile, enhancing computation efficiency through redundancy elimination, coupled with technology feature size scaling, can elevate the vulnerability to aging, reducing the lifetime resilience of DNN accelerators. Previously, designers relied on conservative guard bands to prolong the lifetime of CMOS devices, albeit at the expense of performance loss. This paper proposes the serial processing approach for neural networks based on the redundant number system, which improves lifetime resilience without losing accuracy or performance but, with a few area and power overheads. We explore the number-system effect on BTI (Bias Temperature Instability) stress and consequent aging degradation. Experimental results of DNNs execution illustrate that the proposed computing approach mitigates stress by 36% on average leading to a 35.5% higher lifetime over the baseline.