https://doi.org/10.5573/JSTS.2024.24.1.1

(Minjeong Ryu) ; (Woo Young Choi)

The dependency of silicon-germanium (SiGe) tunnel field-effect transistors (TFETs) on surface stoichiometry is investigated in terms of ambipolar conduction behavior. According to the device simulation results, as the Ge mole fraction of SiGe TFETs increases, p-type TFETs show better performance improvement than n-type ones owing to the SiGe band alignment. Thus, pull-up hole current becomes stronger than pull-down electron one in the case of ambipolar SiGe TFET-based complementary-like logic circuits. The simulated inverters with 50-% Ge content exhibit ~82× lower pull-up and ~9× lower pull-down delays, respectively, than those with pure Si.

https://doi.org/10.5573/JSTS.2024.24.1.8

(Hongsu Byun) ; (Safdar Jamil) ; (Junghyun Ryu) ; (Sungyong Park) ; (Myungcheol Lee) ; (Sung-Soon Park) ; (Youngjae Kim)

While commercially available Computational Storage Drives (CSD) have appeared, it is challenging to build a CSD array-based storage system due to the lack of storage provisioning tools determining the performance and cost-effectiveness of a storage system with CSDs. Therefore, CSDPLAN, a storage provisioning tool to find the number of performance-efficient CSDs when building a storage system with CSD, has been proposed. However, the effectiveness of CSDPLAN has only been evaluated using specific big data analysis workloads, which are not computationally intensive. In this work, we extend CSDPLAN to propose CSDPLAN-EC, a CSD provisioning tool for building storage systems with computationally intensive erasure coding offloaded to CSDs. Our evaluation shows that the optimal number of CSDs running erasure coding in a storage system is 5 and that it decreases to 1 when the computational power of the CSDs is improved by a factor of 5.

https://doi.org/10.5573/JSTS.2024.24.1.18

(Chang Young Lim) ; (Yeon Seok Kim) ; (Min-Woo Kwon)

Dynamic Random Access Memory is critical to computing for its speed and cost-effective capacity. As the demand for high-capacity memory grows, DRAM is being scaled down. However, reduced cell distances cause electrical disturbances between cells, resulting in 1-row hammer. This leads to abnormal operation and security risks. Therefore, 1-row Hammer is a major issue in modern DRAM technology. In this paper, we study the principle and impact of 1-row Hammer in DRAM, with a focus on D0 failures, a type of 1-row Hammer that causes stored data to transition from 0 to 1 due to repeated access. The mechanism involves the electron capture and diffusion of electrons affected by interfacial traps and device structures. To investigate the D0 failure, we reproduced the 1-row hammer using mixed mode to evaluate the effects on the interfacial trap and device structure changes. This research serves to improve understanding of row hammer and suggests a mitigation strategy using nitride layer. The proposed structure improves the D0 failure by about 70%, effectively improving the security vulnerability of DRAM.

https://doi.org/10.5573/JSTS.2024.24.1.25

(Shogo Maeda) ; (Shinsaku Kawabata) ; (Itsuki Nagase) ; (Ali Baratov) ; (Masaki Ishiguro) ; (Toi Nezu) ; (Takahiro Igarashi) ; (Kishi Sekiyama) ; (Suguru Terai) ; (Keito Shinohara) ; (Melvin John F. Empizo) ; (Nobuhiko Sarukura) ; (Masaaki Kuzuhara) ; (Akio Yamamoto) ; (Joel T. Asubar)

We have compared the electrical performance of a proposed normally-off GaN-based MIS-HEMTs employing ultrathin AlGaN barrier layer in the channel with those of conventional recessed-gate structure MIS-HEMTs. The proposed device exhibited much less density of interface states extracted from the measured capacitance-voltage characteristics, suggesting improved Al2O3/AlGaN interface. For corresponding three-terminal transistors, while the conventional reference device exhibited poor control of gate-to-source voltage on drain current with about 3 V hysteresis in the transfer curves, the proposed device showed well-behaved subthreshold characteristics with only 0.8 V hysteresis. Furthermore, the proposed device showed a much higher VTH of +5 V compared to +1 V of the conventional reference device.

https://doi.org/10.5573/JSTS.2024.24.1.33

(Myeongho Park) ; (Kichan Kim) ; (Seungyeon Oh) ; (Il Hwan Cho)

In this study, we investigate the temperature-dependent behavior of a double-gate feedback field effect transistors (FBFETs) device exhibiting steep switching characteristics across a range of temperatures (300 K to 400 K). We analyze the temperature characteristics using technology computer-aided design (TCAD) simulations. FBFETs are semiconductor devices operating on a positive feedback loop, where electrons and holes in the channel region modulate the energy state of the potential barrier and wall. FBFETs demonstrate excellent subthreshold swing and a high on/off ratio, attributed to the positive feedback phenomenon, resulting in ideal switch characteristics. In the simulation results, it is observed that as the temperature increases, the on-current (ION), off-current (IOFF), and on-voltage (VON) all increase, while the on/off current ratio decreases. Furthermore, the operation at high temperatures can be maintained by adjusting the fixed gate voltage. Through the simulation results, we qualitatively examine the variation in various device parameters with temperature changes in FBFETs and provide a detailed discussion.

https://doi.org/10.5573/JSTS.2024.24.1.41

(Bongsu Kim) ; (Seung-Myeong Yu) ; (Jongchan An) ; (Gwangmyeong An) ; (Junyoung Song)

This paper presents a high power supply rejection ratio (PSRR) and a method to achieve stability for low-dropout (LDO) regulators, an essential system-on-chip (SoC) component. The feedforward method improves the PSRR in the LDO regulator by adjusting the output voltage with a compensation signal which is proportional to the power supply noise. Also, the proposed current sensing is incorporated into the LDO regulator's design to ensure stability. The proposed LDO regulates the output at 1 V from a 1.2 V supply and has been implemented based on a 28 nm CMOS process. Compared with a conventional LDO, the simulated PSRR has a -38 dB enhancement at 100 kHz and shows low overshoot and undershoot.

https://doi.org/10.5573/JSTS.2024.24.1.47

(Seongjae Cho) ; (Sung-Tae Lee) ; (Soomin Kim) ; (Hyungcheol Shin)

Recently, existing software-based artificial intelligence technology is being implemented through hardware to improve area and energy efficiencies. Thus, there might be various performance indicators, but power efficiency is an important criterion for evaluating the performance of artificial intelligence chips. Currently, frequently used power efficiency indicators are for all-circuit-based artificial intelligence semiconductor chips, and for the cell-level technology-based artificial intelligence chips that can maximize power efficiency, it is difficult to use the existing indicators as they are. This study presents a practical indicator for evaluating power efficiency when implementing memory cell-based artificial intelligence semiconductor chips. Unlike conventional methodologies, the proposed performance indicators provide a clearer picture of power efficiency changes depending on what type of memory cell is used. Furthermore, the number of multiplicate-and-accumulate (MAC) operations and the number of memory cells cancel each other in the process of deriving the index, which can be a more significant indicator in the memory technology perspective in the sense that it has a greater dependence on the electrical characteristics of the memory cells themselves than on array density.

https://doi.org/10.5573/JSTS.2024.24.1.55

(ByungJun Kim) ; (Han-Gyeol Mun) ; (Shinwoong Kim) ; (JongMin Lee) ; (Jae-yoon Sim)

This work introduces a configurable lattice-based post-quantum cryptography processor designed specifically for lightweight IoT devices. It accelerates the computation of Key-Encapsulation Mechanism (KEM) and Digital Signature Algorithm (DSA) based on module learning with errors algorithm (MLWE). In order to minimize both hardware cost and energy consumption, the processor incorporates a Barrett reduction algorithm method for efficient number-theoretic transform calculations and implements real-time processing for polynomial sampling. The chip is fabricated on a 28 nm CMOS technology process. It achieves the state-of-the-art power efficiencies and latency in MLWE-based PQC.