Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2024-12 (Vol.24 No.06)
  4. 10.5573/JSTS.2024.24.6.540
XML PDF INFO REF

References

1 
J. Kim et al., "A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS," 2018 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 102-104.DOI
2 
Z. Toprak-Deniz et al., "6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 122-124.DOI
3 
J. Im et al., "6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 116-118.DOI
4 
M. Choi et al., "8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 128-130.DOI
5 
Y. Segal et al., "A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 114-116.DOI
6 
K. Sheng, W. Gai, Z. Feng, H. Niu, B. Ye and H. Zhou, "6.7 A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 120-122.DOI
7 
J. Yang et al., "6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 122-124.DOI
8 
M. Cusmai et al., "7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 126-128.DOI
9 
IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std1596.3-1996, 1996.URL
10 
J. Poulton et al., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.DOI
11 
A. Roshan-Zamir, O. Elhadidy, H. -W. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sept. 2017.DOI
12 
DDR4, JEDEC Standard JESD79-4C, Sep. 2012.URL
13 
Y. -C. Cho et al., "A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application," 2013 Symposium on VLSI Circuits, Kyoto, Japan, 2013, pp. C240-C241.URL
14 
D. U. Lee et al., "25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 432-433.DOI
15 
V. Stojanovic et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005.DOI
16 
X. Zheng et al., "A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 7, pp. 1864-1876, July 2020.DOI
17 
Y. -U. Jeong, H. Park, C. Hyun, J. -H. Chae, S. -H. Jeong and S. Kim, "A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1278-1287, April 2021.DOI
18 
G. Steffan et al., "6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 116-117.DOI
19 
E. Groen et al., "10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture," in IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 30-42, Jan. 2021.DOI
20 
Y. Oh et al., "A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology," in IEEE Transactions on Circuits and Syst. II, 2024.DOI
21 
Behad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2017.URL