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  1. (Department of Electronic Engineering, Hanyang University, Seoul, Korea)



Current-mode driver, gain-boosting, output impedance, tailless driver, four-level pulse-amplitude modulation (PAM-4)

I. Introduction

With the advent of the AI era, there has been an explosive increase in data traffic. Consequently, research into high-speed serial links is underway not only in data centers but also in chip-to-chip interfaces for personal devices, making the demand for higher data rates more urgent than ever before. Various high-speed serial link research has continuously increased data transmission speeds over time [1-8], as shown in Fig. 1. To facilitate faster data transmission, various approaches have been employed to implement drivers in transmitters. Historically, push-pull current drivers which are utilized in low-voltage differential signaling were announced, and over time, current-mode drivers such as current-mode logic and tailless drivers, as well as voltage-mode drivers such as N-over-N drivers and CMOS drivers, have been developed to better suit specific applications [9-11]. In scenarios utilizing single-ended signaling and low-power applications like memory interfaces, voltage-mode drivers distinguished by terminations such as pseudo-open drain (POD) and low-voltage swing termination logic (LVSTL) have been employed [12,13]. Recently, in the context of high-bandwidth memory (HBM), which prioritizes high bandwidth over speed, unterminated high-speed logic-based voltage-mode drivers have garnered significant attention for their ability to achieve high bandwidth [14].

Amidst efforts to broaden bandwidth through various circuit technologies and advanced processes, a method called pulse amplitude modulation (PAM) has been proposed [15]. The conventional non-return-to-zero (NRZ) method transmits 1 bit of data per 1 unit interval (UI) using two signal levels. PAM divides signal levels into multiple levels, allowing for the transmission of multiple bits within 1 UI. For instance, PAM-4 transmits 2 bits of data by sending one of four data levels within 1 UI. Furthermore, the fact that the Nyquist frequency of the signal is halved reduces the loss incurred by the channel significantly, depending on the channel environment, which is also an advantage [16].

In this paper, we represent a PAM-4 tailless current-mode driver for short-reach applications. The tailless driver is implemented with an output impedance enhancing technique in a 14-nm FinFET process. The driver operates in 24-Gb/s PAM-4 with an energy efficiency of 2.513 pJ/bit and achieves output impedance boosting about 100% in output voltage operating range compared to conventional tailless driver structure.

The organization of this paper is as follows. Section II compared the various transmit drivers. Section III shows the proposed tailless driver circuit implementation. Sections IV and V show the measurement results and conclusion.

Fig. 1. High-speed serial link trends [1-8].

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II. Review of The Various High-speed Transmit Driver Structures

High-speed transmit driver fundamentally transmits data by applying signals to the channel. A critical aspect of this process is impedance matching with the channel. The channel can be regarded as a transmission line, depending on the ratio between the length of the channel and the frequency of the transmitted signal. Achieving good signal integrity requires matching with the channel’s characteristic impedance. Transmit drivers can be categorized into voltage mode and current mode based on their impedance-matching implementation, as shown in Fig. 2. Voltage-mode drivers utilize Thevenin equivalent series termination for output impedance matching. This method relies on the driver’s own output impedance, necessitating low output impedance. However, achieving precise impedance matching can be challenging due to process, voltage, temperature (PVT) variation, and various external factors. In contrast, current-mode drivers employ Norton equivalent parallel termination. Impedance matching in these drivers is achieved via a termination resistor, requiring the driver’s output impedance to be high. Current-mode drivers are advantageous as they allow for better impedance matching as the output impedance increases, without the need for finely adjusting the output impedance value.

Fig. 2. High-speed transmit driver termination scheme for (a) voltage mode; (b) current mode.

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In voltage-mode drivers, the structure varies depending on output swing size, as shown in Fig. 3. In applications where a small swing is acceptable, an N-over-N driver structure is employed [10]. The driver’s output supply voltage is adjusted via low drop-out regulators to a value smaller than the common supply voltage of the chip, controlling the output swing size. Termination is implemented using NMOS transistors through the pre-driver’s supply voltage. A prominent application example is LVSTL interface for low-power memory applications [13]. When aiming for a larger swing, CMOS structure is utilized [11]. Termination impedance is adjusted by controlling slices composed of CMOS transistors and series resistors. Since the output impedance in voltage-mode drivers is implemented by a combination of transistors and resistors, impedance matching becomes challenging during the transition of output voltages, and due to the variation in output voltage levels, precise impedance matching requires additional circuits such as ZQ calibration [17]. However, in very short-channel environments like HBM, termination may not be necessary, allowing for the implementation of high-speed transmitters with reduced power consumption [14].

Fig. 3. Conventional voltage-mode driver structure of (a) N-over-N driver; (b) CMOS driver.

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Current-mode driver allows for fast transmission due to constant activation of the current source, saving switching time. Additionally, the driver’s output swing control and pre-driver implementations are relatively straightforward. However, a notable drawback is static current consumption. Frequently used representative structures of current-mode drivers including push-pull, current-mode logic (CML), and tailless structures are depicted in Fig. 4. Push-pull driver employs two current sources and transmits data through current path switching. While it offers the advantage of reduced current consumption due to termination with the same output swing, it may require a significant pre-driver swing. Moreover, it occupies a large voltage headroom due to its two current sources and necessitates common-mode feedback. It has previously been referred to as low-voltage differential signals (LVDS) [9]. CML driver typically features a differential structure with load resistors. It is widely used in high-speed transmitters. The tail current source is always active, reducing switching time, but still consumes voltage headroom. To address these issues, a tailless current-mode driver structure has been proposed [18].

Fig. 4. Conventional current-mode driver: (a) push-pull driver; (b) CML driver; (c) tailless driver.

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Tailless current-mode driver structure consists of switching transistors and cascode transistors which are flipped from input transistors and tail current source in the CML driver. Under the same power supply voltage, as the gate-source voltage of the input transistors increases, the tailless driver can generate the same amplitude of output swing as the CML driver using smaller transistors [20]. This proves advantageous in advanced process nodes where increasing supply voltage is challenging. Additionally, a smaller input transistor size reduces parasitic capacitance which is better for high-speed data transmission. In tailless drivers, to achieve high-speed operation, the size of the cascode transistor can be designed small, and the overdrive voltage can be set high. In such cases, the cascode transistor may operate in the linear region, leading to poor impedance-matching characteristics. To address this issue, [4] attempted an improvement by using a pull-up current source. By increasing the output common-mode voltage, they improved impedance matching characteristics while accepting the increased loading on the output node.

III. Circuit Implementation

1. PAM-4 Tailless Current-mode Driver

PAM-4 driver can be implemented through various high-speed transmit driver structures described before. When implementing a PAM-4 driver using a voltage-mode driver, the output impedance must be combined with the LSB driver, which is twice that of MSB, and the parallel output impedance of both must be matched to the characteristic impedance of channel configuration which is usually 50 ${\Omega}$. Therefore, precise output impedance calibration is required for each driver. To implement PAM-4, the output impedance must be matched at each PAM-4 output level. Additionally, the complex structure of the pre-driver is a factor that impairs the overall power efficiency of the driver. PAM-4 signaling has a disadvantage in terms of signal-to-noise ratio (SNR) compared to NRZ signaling [19]. Voltage-mode drivers have a disadvantage in PAM-4 with low SNR due to the limitation of output swing size by the driver’s supply voltage.

Implementing a PAM-4 driver in current mode is relatively straightforward, as it simply requires doubling the driving strength of the MSB slice compared to the LSB slice. If the output impedance of the driver is sufficiently high, a simple parallel resistor can implement termination without being constrained by the output voltage level. Additionally, it facilitates high-speed signal transmission through reduced switching time and allows for easy adjustment of output swing amplitude by controlling current. However, to achieve a large output swing, the driver’s supply voltage must be increased, and the increased voltage level may cause gate-oxide breakdown in advanced process transistors, especially in cases where the output swing is very large in the CML driver depicted in Fig. 4(b).

In contrast, in the tailless current-mode structure which is depicted in Fig. 4(c), applying an appropriate bias voltage to the gate of the cascode transistor can protect the input transistors from large output swings. Furthermore, under the same power supply voltage configuration, the tailless driver can input a larger gate-source voltage to the input transistors than the CML driver and can flow a larger current at the same size of the input transistors, thereby increasing current density. Therefore, it can be considered more suitable for high-speed operation than a conventional CML driver.

A larger output swing of the driver can be advantageous from an SNR perspective. To achieve this, a high supply voltage can be used to obtain a large output swing. However, if the output swing size increases under a constant supply voltage, the output common-mode voltage decreases, causing the transistor to operate in the linear region, which can degrade impedance-matching characteristics. Additionally, in CML driver structures with high supply voltage, such as in [7], gate breakdown due to leakage current can occur, requiring techniques like the current bleeder to address this issue. To avoid these problems, we performed transistor sizing to achieve a reasonable output swing size at a relatively low supply voltage. The bias voltage of the cascode transistors is set to an appropriate value to prevent gate-oxide breakdown for finFET process. This approach allows us to maintain good impedance-matching characteristics and reliability. Additionally, by employing a tailless driver structure designed to operate at a low voltage without a current source, we were able to eliminate the need for additional techniques such as the current bleeder, thereby reducing design complexity and layout area.

Combining these features, a PAM-4 driver was implemented as a tailless current-mode as shown in Fig. 5. The PAM-4 driver consists of MSB and LSB slices in a tailless current-mode driver structure, along with an output network composed of termination resistors, T-coils, and ESD protection diodes.

Fig. 5. PAM-4 tailless current-mode driver.

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2. Output Impedance Enhancing Technique

To achieve superior impedance matching in the current-mode driver, it is essential to maximize the driver’s output impedance. One method to increase the output impedance of a transistor is by increasing the channel length of the transistor. In the case of conventional CML drivers, the input transistors perform a switching operation, while the current source remains constantly active, determining the swing size. Designing the current source of the CML driver with long channel transistors results in obtaining high output impedance. In contrast, in the tailless driver, the output swing size can be adjusted by controlling the gate bias of the cascode transistors. However, due to the parasitic capacitance of the cascode transistors directly connected to the output node, this transistor must be implemented with short-channel devices, resulting in lower output impedance compared to the CML driver. As a result, the output impedance decreases compared to CML drivers, adversely affecting impedance matching, which is determined by the parallel combination value of the termination resistor and the driver output impedance.

To address these issues, the gain-boosting technique was adopted for the tailless driver, and the corresponding structure is depicted in Fig. 6. By utilizing the gain-boosting technique, the output impedance can be increased without adding a cascode device [21]. This approach prevents additional consumption in voltage headroom and output swing size is maintained. The gain-boosting circuit senses the drain node voltage of the input transistor. It applies negative feedback to the gate of the cascode transistor through a source follower and common source stage. Consequently, the output impedance is amplified by the loop gain of the feedback loop, enhancing the impedance-matching characteristics.

Fig. 6. Output impedance boosting circuit.

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IV. Measurement Results

The driver prototype of the PAM-4 tailless current-mode transmit driver was fabricated using a 14-nm FinFET process and the chip micrograph is shown in Fig. 7. On the chip’s output pads, ESD diodes of about 500 fF are connected for ESD protection and can be considered capacitive loads.

The measurement setup is depicted in Fig. 8(a). The prototype chip was mounted on a test PCB (FR-4) using chip-on-board (COB) technology, followed by wire bonding. A 12-Gb/s MSB and LSB PRBS7 data pattern was applied to the chip through a bit pattern generator (SHF 12124B), which operates via a 12-GHz clock from an Analog Signal Generator (Keysight E8257C). The signals applied to the chip were transmitted to the driver through an internal buffer. The output signal was measured using a sampling oscilloscope, after passing through the bonding wire and test PCB trace. The channel loss, excluding the bonding wire loss, measured at 6 GHz was -1.2 dB, as depicted in Fig. 8(b).

The driver operates at 24 Gb/s, and the corresponding PAM-4 eye diagram can be seen in Fig. 9. The magnitude of the output differential signal is 492 mV, and the worst-case PAM-4 eye has a vertical opening of 44.6 mV and a horizontal opening of 35.54 ps. To verify the effectiveness of the output impedance enhancing technique, the current flowing through the output node was measured at various output voltages, and the calculated output impedance values are presented in Fig. 10. This demonstrates an improvement in output impedance. The measured performance is summarized in Table 1.

Fig. 7. Chip micrograph.

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Fig. 8. (a) Measurement setup; (b) measured channel loss.

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Fig. 9. Measured 24-Gb/s differential output eye diagram.

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Fig. 10. Driver current as a function of Vout without and with output impedance boosting technique.

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Table 1. Performance summary (measurements)

Process

14-nm FinFET

Circuits

Transmit driver and buffer

Max. Data Rate

24 Gb/s @ 1.3 V

Eye Opening

44.6mV, 35.54 ps

@ 24 Gb/s, 1.3 V

Power Consumption

60.3 mW @ 24 Gb/s

Chip Area

250 mm × 136 mm

V. Conclusions

A PAM-4 tailless current-mode driver was implemented using an output impedance enhancing technique. The vulnerability of vanilla tailless drivers, which is the low output impedance, was improved by utilizing a gain-boosting technique, thus enhancing the impedance matching performance with the transmission line. The chip was fabricated using a 14-nm FinFET process, and the driver’s output supply voltage was set to 1.3 V. An eye-opening at 24 Gb/s PAM-4 was achieved without the need for FFE or other equalizing circuits, and the energy efficiency was 2.513 pJ/bit. Additionally, the output impedance enhancing technique improved the driver’s output impedance by approximately 100 % within the voltage range of the output node.

ACKNOWLEDGMENTS

The research is sponsored in part by Samsung Electronics (Chip Interconnect Solutions), the Technology Innovation Program (RS-2024-00416689) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), and Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2024)-RS-2023-00253914) grant funded by the Korea government(MSIT).

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Yunseong Jo
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Yunseong Jo received his B.S. degree in electrical engineering from Hanyang University, Seoul, South Korea, in 2020, where he is currently pursuing the integrated M.S. and Ph.D. degree in electronic engi-neering. His research interests include high-speed serial link, memory interface, analog and mixed-signal (AMS) circuit design automation, and automatic layout generation of full custom IC.

Jaeduk Han
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Jaeduk Han received his B.S. and M.S. degrees in electrical engi-neering from Seoul National University, Seoul, South Korea, in 2007 and 2009, respectively, and the Ph.D. degree in electrical engi-neering and computer sciences from the University of California at Berkeley, Berkeley, CA, USA, in 2017, He is currently an Assistant Professor of electronic engineering with Hanyang University, Seoul. He has held various internship and full-time positions at TLI, Seongnam, South Korea; Altera, San Jose, CA, USA; Intel, Hillsboro, OR, USA; Xilinx, San Jose; and Apple, Cupertino, CA, USA, where he worked on digital, analog, and mixed-signal integrated circuit designs and design automations. His research interests include high-speed analog and mixed-signal (AMS) circuit design and automation.