Min, S. R., Lee, S. H., Park, J., Kim, G. U., Kang, G. E., Heo, J. H., Yoon, Y. J.,
Seo, J. H., Jang, J., Bae, J. H., and Kang, I. M. “Simulation of CMOS logic inverter
based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET
and its electrical characteristics.” Current Applied Physics, pp. 106-115, vol.43,
Nov. 2022.
