I. INTRODUCTION

Recently, as the size of the semiconductor devices has decreased, the short-channel effects (SCEs) has appeared in the metal-oxide-semiconductor field-effect transistors (MOSFETs) ^[1-4]. Also, a subthreshold swing (SS) of the MOSFET is limited to 60 mV/decade at a room temperature. However, because a tunneling field-effect transistor (TFET) operates by the band-to-band-tunneling (BTBT), it has the immunity to the SCEs and the SS under 60 mV/dec ^[5-8]. Also, the poly-Si can be applied to 3-dimensional vertical stacking, and is advantageous in terms of manufacturing process technology. In addition, it can replace the silicon-on-insulator (SOI) structure of the high fabrication cost. In this study, the multiple nanosheet structure based on the polycrystalline silicon (poly-Si) is used to improve the I$_{\mathrm{on}}$ of the TFET and to suppress the SCE. These multiple nanosheet tunneling field-effect transistors (MNSTFETs) based on the poly-Si can compensate for the low I$_{\mathrm{on}}$ of TFET. Because the poly-Si is adapted in these devices, it is important to analyze the grain boundary (GB)’s effects. ^[9,10]

In this study, we present the electrical performances of the MNSTFETs depending on the GB-locations. Also, we compare the electrical characteristics of the MNSTFETs and the MNSMOSFETs based on the poly-Si ^[11].

II. DEVICE STRUCTURE AND SIMULATION METHOD

Fig. 1 shows the 3-dimensional view and the cross-sectional view of the MNSTFET based on the poly-Si ^[12]. The poly-Si was used as a material for the nanosheet channels, and the gate length (L$_{\mathrm{g}}$), the nanosheet width (W$_{\mathrm{sh}}$), and the nanosheet total width (W$_{\mathrm{total}}$) are 16, 30, and 76 nm, respectively. The gate insulator (HfO$_{2}$/SiO$_{2}$) thickness (T$_{\mathrm{ox}}$) is 1.1/0.3 nm, and SiO$_{2}$ was used as the interfacial layer. The doping concentrations of the source, channel, and drain regions are 1 ${\times}$ 10$^{20}$ cm$^{-3}$ (p-type), 1 ${\times}$ 10$^{16}$ cm$^{-3}$ (n-type), and 1 ${\times}$ 10$^{19}$ cm$^{-3}$ (n-type), respectively. The parameters of the proposed device are summarized in Table 1. The I$_{\mathrm{on}}$ is defined as the drain current (I$_{\mathrm{DS}}$) when the gate voltage (V$_{\mathrm{GS}}$) is 1.0 V and the drain voltage (V$_{\mathrm{DS}}$) is 0.7 V. The I$_{\mathrm{off}}$ is defined as the I$_{\mathrm{DS}}$ when the V$_{\mathrm{GS}}$ = 0.0 V and the V$_{\mathrm{DS}}$ = 0.7 V. The V$_{\mathrm{T}}$ is defined as the gate voltage when the I$_{\mathrm{DS}}$ = 0.1 ${\mu}$A/${\mu}$m. The average of subthreshold swing (SS$_{\mathrm{ave}}$) is defined as the inverse of the average slope between two points where the I$_{\mathrm{DS}}$ is I$_{\mathrm{off}}$ and 0.1 ${\mu}$A/${\mu}$m.

Fig. 2(a) shows the I$_{\mathrm{DS}}$-V$_{\mathrm{GS}}$ simulation curves fitted by the experimental data in ^[13] to accurately implement the tunneling model. The trap distribution in the grain boundary (GB) of the poly-Si was extracted from experimental data from ^[14], as shown in Fig. 2(b). The GB has both the donor-like traps and the acceptor-like traps. This device was simulated by the Sentaurus technology computer-aided design (TCAD) tool. These simulations include the dynamic nonlocal BTBT model, the bandgap narrowing model, the Fermi-Dirac model, the Shockley-Read-Hall recombination model, the trap-assisted Auger recombination model, and the multivalley (MLDA) model to increase the accuracy of the simulation ^[15].

Fig. 1. The 3-dimensional view and the cross-sectional view of the MNSTFET based on the poly-Si.

Fig. 2. (a) The I$_{\mathrm{DS}}$-V$_{\mathrm{GS}}$ simulation curves fitted by the experimental data in[13]to implement the tunneling model. (b) The GB trap distribution extracted from the experimental data in[14].

III. RESULTS AND DISCUSSION

Fig. 3(a)-(f) show the cross-sections of the MNSTFETs based on the poly-Si depending on the GB-locations. These devices have 3 nanosheets and they have 1 GB on each nanosheets except the case (f). Fig. 3(f) shows the device based on the single crystalline silicon without the GB. Fig. 4 is the transfer curves of the MNSTFETs for Fig. 3(a)-(f) cases, which are normalized with the W$_{\mathrm{total}}$. Table 2 summarizes the electrical characteristics of Fig. 4. Fig. 5(a) is the energy band diagrams of the MNSTFETs depending on the GB locations when the V$_{\mathrm{GS}}$ = 1 V. Fig. 5(b) is the energy band diagrams with enlarged the red boxes of Fig. 5(a). In Table 2, the I$_{\mathrm{on}}$ and the V$_{\mathrm{T}}$ in the case of x = 9 nm have the largest difference with 26.8\% and 5.0\%, respectively, compared with the case without the GB. The thicker the tunneling barrier, the more difficult it is for electrons to tunnel. The tunneling barrier for x = 9 nm is the thickest as shown as in Fig. 5(a) and it makes the I$_{\mathrm{on}}$ smaller and V$_{\mathrm{T}}$ larger. The tunneling barrier is thick because the sharp band peak is created due to electrons trapped in the GB as shown in Fig. 5(b). Therefore, the I$_{\mathrm{on}}$ is the lowest and the V$_{\mathrm{T}}$ is the largest. However, as shown in Fig. 5(b), when the GB location varies from 9 nm to 14, 19, and 24 nm in order, the sharp band peak gradually moves away from the tunneling region. This reduces the interference of the electron flow, so that the I$_{\mathrm{on}}$ increases and the V$_{\mathrm{T}}$ decreases, which is similar to the values in the case without the GB. Fig. 6(a) is the energy band diagrams of the MNSTFETs depending on the GB locations when the V$_{\mathrm{GS}}$ = 0 V. Fig. 6(b) is the energy band diagrams with enlarged the red boxes of Fig. 6(a). As shown in Table 2, the I$_{\mathrm{off}}$ and the average of subthreshold swing (SS$_{\mathrm{ave}}$) in the case of x = 24 nm have the largest difference of 49.2\% and 38.7\%, respectively, compared with the case without the GB. This is because the trap-assisted-tunneling (TAT) occurs when x = 24 nm. Fig. 6(a) shows that when x = 24 nm, it is the region where the TAT can occur. As shown in Fig. 6(b), when x = 24 nm, the energy band rises to the top due to the electrons trapped in the GB. The electrons are tunneled through these traps, and they result in high leakage current at an off-state. And the SS$_{\mathrm{ave}}$ is the largest value of 104.0 mV. Fig. 7(a) and (b) show the distribution of the electrons and holes trapped in the GB of the MNSTFETs when V$_{\mathrm{GS}}$ are 1.0 V and 0.0 V, respectively, depending on the GB locations. The energy band where the GB is located rises because the number of electrons trapped in the GB is larger than the number of holes. Thus, the energy band rises upwards, acting as if a negative voltage is applied.

We have compared the electrical characteristics of MNSTFETs and MNSMOSFETs. Fig. 8 shows the transfer curves of MNSMOSFETs based on the poly-Si depending on the GB-locations. The structure, the materials, and the GB locations of the MNSMOSFETs are the same as those of the MNSTFETs. Their doping concentrations in the source, channel, and drain regions are 1 ${\times}$ 10$^{19}$ cm$^{-3}$ (n-type), 1 ${\times}$ 10$^{17}$ cm$^{-3}$ (p-type), and 1 ${\times}$ 10$^{19}$ cm$^{-3}$ (n-type), respectively. In Fig. 9(a) and (b) compares the SS$_{\mathrm{min}}$ and the SS$_{\mathrm{ave}}$ of the MNSTFETs and the MNSMOSFETs depending on the GB locations. As shown in Fig. 9(a), the SS$_{\mathrm{min}}$’s for the MNSTFETs are smaller than those for the MNSMOSFETs. This is because the TFET uses tunneling mechanism and the MOSFET uses drift mechanism. Also, as shown in Fig. 9(b), the SS$_{\mathrm{ave}}$’s of MNSTFETs has a smaller effect depending on the GB locations than those of the MNSMOSFETs except for the case of x = 24 nm. In the case of MOSFET, the electrons trapped in the GB act the same as applying a negative voltage to the gate, interrupting channel formation ^[11]. And it makes the SS$_{\mathrm{ave}}$ deviation larger depending on the GB locations. But, in the case of TFET, it is only affected when the GB is located in the TAT region. Therefore, if the GB is not located at 24 nm, the electrical characteristics of the MNSTFET depending on the GB locations are superior to those of the MNSMOSFET.

The poly-Si has the random distribution of the GB. Therefore, it is necessary to compare the characteristics of the MNSTFET and the MNSMOSFET by varying the GB location in each sheet. Fig. 10(a) and (b) show the histogram of the V$_{\mathrm{T}}$ and the SS$_{\mathrm{ave}}$ of the MNSTFETs and the MNSMOSFETs extracted from 125 (= 5 ${\times}$ 5 ${\times}$ 5) samples. The GB is located at one of the following locations on each sheet: 4, 9, 14, 19, and 24 nm. The total number of sheets of this device is 3, and each sheet has one GB. Fig. 10(c) shows a histogram of SS$_{\mathrm{ave}}$ of the MNSTFETs and the MNSMOSFETs extracted from 64 (= 4 ${\times}$ 4 ${\times}$ 4) samples except for the case of x = 24 nm in Fig. 10(b). The GB is located at one of the following locations on each sheet: 4, 9, 14, and 19 nm. The standard deviation (SD) is a value indicating how far the data are spread around the mean. The relative standard deviation (RSD) is the SD divided by the mean and multiplied by 100. The small RSD means that the SD is relatively small compared with the mean, so the

dispersion is small. In Fig. 10(a), the means of the extracted V$_{\mathrm{T}}$’s of the MNSTFETs and the MNSMOSFETs are 0.412 V and 0.206 V, respectively. The SDs are 3.90 mV and 8.31 mV, respectively. The RSDs are 0.95\% and 4.03\%, respectively. For the same reason as described for SS$_{\mathrm{ave}}$ in Fig. 9(b), the electrons trapped in the GB interfere with channel formation. So, the SD and RSD of the MNSTFET are smaller than those of the MNSMOSFET. In Fig. 10(b), the means of the extracted SS$_{\mathrm{ave}}$’s of the MNSTFETs and the MNSMOSFETs are 72.7 mV/dec and 70.5 mV/dec, respectively. The SDs are 7.08 mV/dec and 4.00 mV/dec, respectively. The RSDs are 9.75\% and 5.67\%, respectively. The SS$_{\mathrm{ave}}$’s of the MNSTFETs have a larger dispersion than those of the MNSMOSFETs. However, as shown in Fig. 10(c), except for the case of x = 24 nm, the means of the extracted SS$_{\mathrm{ave}}$’s of the MNSTFETs and the MNSMOSFETs are 67.2 mV/dec and 72.4 mV/dec, respectively. The SDs are 1.50 mV/dec and 4.16 mV/dec, respectively. The RSDs are 2.24\% and 5.74\%, respectively. If the GB is not located at 24 nm, the MNSTFET is better than the MNSMOSFET in terms of the I$_{\mathrm{off}}$, the V$_{\mathrm{T}}$, and the SS$_{\mathrm{ave}}$. Therefore, when fabricating the MNSTFET device, it is important to control the process so that the GB is not located in the drain region.

Fig. 3. (a) to (f) The cross-sections of the MNSTFET based on the poly-Si depending on GB-locations.

Fig. 4. The transfer curves of the MNSTFET based on the poly-Si depending on GB-locations.

Fig. 5. (a) The energy band diagram of the MNSTFET depending on GB-locations when V$_{\mathrm{GS}}$ is 1 V; (b) The energy band diagram with enlarged of the red boxes in Fig. 5(a). The energy bands are extracted at the 2 nm below the gate insulator along the A-A’ line.

Fig. 6. (a) The energy band diagram of the MNSTFET depending on GB-locations when V$_{\mathrm{GS}}$ is 0 V; (b) The energy band diagram with enlarged of the red boxes in Fig. 6(a).

Fig. 7. The distribution of electrons and holes trapped in the GB of the MNSTFET depending on GB-locations when V$_{\mathrm{GS}}$ is (a) 1 V; (b) 0 V, respectively. The electrons and holes trapped in GB are extracted at the 2 nm below the gate insulator along the A-A’ line.

Fig. 8. The transfer curves of the MNSMOSFET based on the poly-Si depending on GB-locations.

Fig. 9. (a) SS$_{\mathrm{min}}$; (b) SS$_{\mathrm{ave}}$ of the MNSTFET and the MNSMOSFET based on the poly-Si depending on GB-locations.

Fig. 10. The histograms of (a) the V$_{\mathrm{T}}$’s; (b) the SS$_{\mathrm{ave}}$’s of the MNSTFETs and the MNSMOSFETs extracted from 125 (= 5 ${\times}$ 5 ${\times}$ 5) samples; (c) The histogram of SS$_{\mathrm{ave}}$’s of the MNSTFETs and the MNSMOSFETs extracted from 64 (= 4 ${\times}$ 4 ${\times}$ 4) samples except for the case when the GB is at 24 nm in Fig. 10(b).

IV. CONCLUSIONS

This study showed the transfer performances depending on the GB-locations within a sheet in the MNSTFET based on the poly-Si. As a result of the analysis, the largest V$_{\mathrm{T}}$ was shown for the case of x = 9 nm, and the largest SS$_{\mathrm{ave}}$ was shown for the case of x = 24 nm due to the TAT. In addition, the electrical characteristics of 125 samples of the MNSTFETs were compared with the MNSMOSFETs. If the GB was not located at 24 nm, the MNSTFET was better than the MNSMOSFET in terms of the I$_{\mathrm{off}}$, the V$_{\mathrm{T}}$, and the SS$_{\mathrm{ave}}$. Consequently, this simulation showed that the MNSTFET has smaller effect on the GB location than the MNSMOSFET.